PIC16F737-I/SP Microchip Technology Inc., PIC16F737-I/SP Datasheet - Page 38

• Manufacturer Part Number: PIC16F737-I/SP
• Description: 28 PIN, 7 KB FLASH, 368 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F737-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F7X7
4.5.1
Using the internal oscillator as the clock source can
eliminate the need for up to two external oscillator pins,
after which it can be used for digital I/O. Two distinct
configurations are available:
• In INTIO1 mode, the OSC2 pin outputs F
• In INTIO2 mode, OSC1 functions as RA7 and
REGISTER 4-1:
DS30498C-page 36
while OSC1 functions as RA7 for digital input and
output.
OSC2 functions as RA6, both for digital input and
output.
bit 7-6
bit 5-0
INTRC MODES
OSCTUNE: OSCILLATOR TUNING REGISTER (ADDRESS 90h)
Unimplemented: Read as ‘0’
TUN<5:0>: Frequency Tuning bits
011111 = Maximum frequency
011110 =
•
•
•
000001 =
000000 = Center frequency. Oscillator module is running at the calibrated frequency.
111111 =
•
•
•
100000 = Minimum frequency
bit 7
Legend:
R = Readable bit
-n = Value at POR
U-0
—
U-0
—
OSC
/4,
R/W-0
TUN5
W = Writable bit
‘1’ = Bit is set
R/W-0
TUN4
frequency. The INTRC clock will reach the new
frequency
4.5.2
The internal oscillator’s output has been calibrated at the
factory but can be adjusted in the application. This is
done by writing to the OSCTUNE register (Register 4-1).
The tuning sensitivity is constant throughout the tuning
range. The OSCTUNE register has a tuning range of
±12.5%.
When the OSCTUNE register is modified, the INTOSC
and INTRC frequencies will begin shifting to the new
8 * 32 s = 256 s); the INTOSC clock will stabilize
within 1 ms. Code execution continues during this shift.
There is no indication that the shift has occurred. Oper-
ation of features that depend on the 31.25 kHz INTRC
clock source frequency, such as the WDT, Fail-Safe
Clock Monitor and peripherals, will also be affected by
the change in frequency.
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TUN3
OSCTUNE REGISTER
within
8 clock
R/W-0
TUN2
 2004 Microchip Technology Inc.
cycles
x = Bit is unknown
R/W-0
TUN1
(approximately
R/W-0
TUN0
bit 0