PIC16F737-I/SP Microchip Technology Inc., PIC16F737-I/SP Datasheet - Page 28

• Manufacturer Part Number: PIC16F737-I/SP
• Description: 28 PIN, 7 KB FLASH, 368 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F737-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F7X7
2.2.2.6
The PIE2 register contains the individual enable bits for
the CCP2 and CCP3 peripheral interrupts.
REGISTER 2-6:
DS30498C-page 26
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PIE2 Register
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS 8Dh)
bit 7
OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled
CMIE: Comparator Interrupt Enable bit
1 = Enabled
0 = Disabled
LVDIE: Low-Voltage Detect Interrupt Enable bit
1 = LVD interrupt is enabled
0 = LVD interrupt is disabled
Unimplemented: Read as ‘0’
BCLIE: Bus Collision Interrupt Enable bit
1 = Enable bus collision interrupt in the SSP when configured for I
0 = Disable bus collision interrupt in the SSP when configured for I
Unimplemented: Read as ‘0’
CCP3IE: CCP3 Interrupt Enable bit
1 = Enables the CCP3 interrupt
0 = Disables the CCP3 interrupt
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend:
R = Readable bit
-n = Value at POR
OSFIE
R/W-0
R/W-0
CMIE
R/W-0
LVDIE
W = Writable bit
‘1’ = Bit is set
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
BCLIE
U-0
 2004 Microchip Technology Inc.
—
2
2
C Master mode
C Master mode
x = Bit is unknown
CCP3IE
R/W-0
CCP2IE
R/W-0
bit 0