PIC16F737-I/SP Microchip Technology Inc., PIC16F737-I/SP Datasheet - Page 70

• Manufacturer Part Number: PIC16F737-I/SP
• Description: 28 PIN, 7 KB FLASH, 368 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F737-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F7X7
5.5
This section is not applicable to the PIC16F737 or
PIC16F767.
PORTE has four pins, RE0/RD/AN5, RE1/WR/AN6,
RE2/CS/AN7 and MCLR/V
ally configureable as inputs or outputs. These pins have
Schmitt Trigger input buffers. RE3 is only available as an
input if MCLRE is ‘0’ in Configuration Word 1.
I/O PORTE becomes control inputs for the micro-
processor port when bit, PSPMODE (TRISE<4>), is
set. In this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs). Ensure ADCON1 is configured for digital I/O. In
this mode, the input buffers are TTL.
Register 5-1 shows the TRISE register which also
controls the Parallel Slave Port operation.
PORTE pins are multiplexed with analog inputs. When
selected as an analog input, these pins will read as ‘0’s.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
TABLE 5-9:
TABLE 5-10:
DS30498C-page 68
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
MCLR/V
Legend:
Note 1:
09h
89h
9Fh
Legend:
Note 1:
Addr
Note:
Name
PORTE
TRISE
ADCON1
PP
PORTE and TRISE Register
Name
/RE3
ST = Schmitt Trigger input, TTL = TTL input
Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.
On a Power-on Reset, these pins are
configured as analog inputs and read as ‘0’.
Bit#
bit 0
bit 1
bit 2
bit 3
PORTE FUNCTIONS
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
ADFM ADCS2 VCFG1
Bit 7
IBF
—
Buffer Type
ST/TTL
ST/TTL
ST/TTL
PP
Bit 6
OBF
ST
—
/RE3, which are individu-
(1)
(1)
(1)
IBOV
Bit 5
Input/output port pin or read control input in Parallel Slave Port mode or analog input.
For RD (PSP mode):
1 = Idle
0 = Read operation. Contents of PORTD register output to PORTD I/O pins (if chip selected).
Input/output port pin or write control input in Parallel Slave Port mode or analog input.
For WR (PSP mode):
1 = Idle
0 = Write operation. Value of PORTD I/O pins latched into PORTD register (if chip selected).
Input/output port pin or chip select control input in Parallel Slave Port mode or analog input.
For CS (PSP mode):
1 = Device is not selected
0 = Device is selected
Input, Master Clear (Reset) or programming input voltage.
—
PSPMODE
VCFG0
Bit 4
—
PCFG3 PCFG2
Bit 3
—
RE3
(1)
FIGURE 5-19:
PORTE Data Direction bits
Bit 2
RE2
Data Bus
WR Port
WR TRIS
RD TRIS
RD Port
Note 1: I/O pins have protection diodes to V
PCFG1
Function
Bit 1
RE1
TRIS Latch
Data Latch
D
D
CK
CK
PCFG0
Bit 0
RE0
Q
PORTE BLOCK DIAGRAM
(IN I/O PORT MODE)
Q
 2004 Microchip Technology Inc.
---- x000
0000 1111
0000 0000
Q
POR, BOR
Value on:
EN
EN
Schmitt
Trigger
D
Buffer
Input
DD
and V
---- x000
0000 1111
0000 0000
Value on
all other
Resets
I/O pin
SS
.
(1)