PIC16F72-I/SP Microchip Technology Inc., PIC16F72-I/SP Datasheet - Page 11

• Manufacturer Part Number: PIC16F72-I/SP
• Description: 28 PIN, 3.5 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F72-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

2.2.2
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
 2002 Microchip Technology Inc.
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h-1Dh
1Eh
1Fh
Legend:
Note
Bank 0
(1)
(1)
(1)
(1)
(1,2)
(1)
1: These registers can be addressed from any bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
3: This bit always reads as a ‘1’.
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
ADRES
ADCON0
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
contents are transferred to the upper byte of the program counter.
Name
SPECIAL FUNCTION REGISTERS
—
—
—
—
SPECIAL FUNCTION REGISTER SUMMARY
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
Timer0 Module’s Register
Program Counter's (PC) Least Significant Byte
Indirect Data Memory Address Pointer
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
Unimplemented
Unimplemented
Unimplemented
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Timer2 Module’s Register
Synchronous Serial Port Receive Buffer/Transmit Register
Capture/Compare/PWM Register (LSB)
Capture/Compare/PWM Register (MSB)
Unimplemented
A/D Result Register
ADCS1
WCOL
Bit 7
IRP
GIE
—
—
—
—
—
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000
SSPOV
ADCS0
PEIE
ADIF
Bit 6
RP1
—
—
—
—
PORTA Data Latch when written: PORTA pins when read
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR0IE
SSPEN
CCP1X
CHS2
Bit 5
RP0
—
—
Write Buffer for the upper 5 bits of the Program Counter
CCP1Y
CHS1
INTE
Bit 4
CKP
TO
—
CCP1M3
SSPM3
SSPIF
CHS0
RBIE
Bit 3
PD
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
GO/DONE
CCP1M2
TMR0IF
CCP1IF
SSPM2
Bit 2
Z
TMR1CS
CCP1M1
TMR2IF
SSPM1
INTF
Bit 1
DC
—
TMR1ON --00 0000
CCP1M0 --00 0000
TMR1IF
SSPM0
ADON
RBIF
Bit 0
C
PIC16F72
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
--0x 0000
xxxx xxxx
xxxx xxxx
---0 0000
0000 000x
-0-- 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 00-0
POR, BOR
Value on
DS39597B-page 9
—
—
—
—
Details on
38,39,41
38,39,41
page:
29,13
43,48
19
18
12
19
21
23
25
18
14
16
31
31
31
35
36
45
37
53
53
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