PIC16F72-I/SP Microchip Technology Inc., PIC16F72-I/SP Datasheet - Page 29

• Manufacturer Part Number: PIC16F72-I/SP
• Description: 28 PIN, 3.5 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F72-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.0
The FLASH Program Memory is readable during nor-
mal operation over the entire V
addressed through Special Function Registers (SFR).
Up to 14-bit wide numbers can be stored in memory for
use as calibration parameters, serial numbers, packed
7-bit ASCII, etc. Executing a program memory location
containing data that forms an invalid instruction results
in a NOP.
There are five SFRs used to read the program and
memory:
• PMCON1
• PMDATL
• PMDATH
• PMADRL
• PMADRH
The program memory allows word reads. Program
memory access allows for checksum calculation and
reading calibration tables.
When interfacing to the program memory block, the
PMDATH:PMDATL registers form a two-byte word,
which
PMADRH:PMADRL registers form a two-byte word,
which holds the 13-bit address of the FLASH location
being accessed. This device has up to 2K words of
program FLASH, with an address range from 0h to
07FFh. The unused upper bits PMDATH<7:6> and
PMADRH<7:5> are not implemented and read as
zeros.
REGISTER 4-1:
 2002 Microchip Technology Inc.
holds
READING PROGRAM MEMORY
bit 7
bit 6-1
bit 0
the
14-bit
PMCON1: PROGRAM MEMORY CONTROL REGISTER 1 (ADDRESS 18Ch)
Reserved: Read as ‘1’
Unimplemented: Read as ‘0’
RD: Read Control bit
1 = Initiates a FLASH read, RD is cleared in hardware. The RD bit can only be set (not cleared)
0 = Does not initiate a FLASH read
bit 7
Legend:
W = Writable bit
R = Readable bit
‘1’ = Bit is set
reserved
R-1
in software.
data
DD
range. It is indirectly
for
U-0
—
reads.
The
U-0
—
U = Unimplemented bit, read as ‘0’
S = Settable bit
‘0’ = Bit is cleared
4.1
The address registers can address up to a maximum of
8K words of program FLASH.
When selecting a program address value, the MSByte
of the address is written to the PMADRH register and
the LSByte is written to the PMADRL register. The
upper MSbits of PMADRH must always be clear.
4.2
PMCON1 is the control register for memory accesses.
The control bit RD initiates read operations. This bit
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the read operation.
U-0
—
PMADR
PMCON1 Register
U-0
—
U-0
—
-n = Value at POR
x = Bit is unknown
PIC16F72
U-0
—
DS39597B-page 27
R/S-0
RD
bit 0