PIC16F72-I/SP Microchip Technology Inc., PIC16F72-I/SP Datasheet - Page 50

• Manufacturer Part Number: PIC16F72-I/SP
• Description: 28 PIN, 3.5 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F72-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F72
9.3
The SSP module in I
functions, except general call support and provides
interrupts on START and STOP bits in hardware to
facilitate firmware implementations of the master func-
tions. The SSP module implements the Standard mode
specifications, as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the RC3/
SCK/SCL pin, which is the clock (SCL), and the RC4/
SDI/SDA pin, which is the data (SDA). The user must
configure these pins as inputs or outputs through the
TRISC<4:3> bits.
The SSP module functions are enabled by setting SSP
Enable bit SSPEN (SSPCON<5>).
FIGURE 9-5:
The SSP module has five registers for I
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly
• SSP Address Register (SSPADD)
The SSPCON register allows control of the I
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
• I
• I
• I
• I
• I
DS39597B-page 48
RC3/SCK/SCL
RC4/
accessible
STOP bit interrupts enabled
STOP bit interrupts enabled
is IDLE
SDA
SDI/
2
2
2
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Slave mode (7-bit address), with START and
C Slave mode (10-bit address), with START and
C Firmware controlled Master operation, Slave
SSP I
Read
Clock
2
Shift
C Mode Operation
MSb
2
2
C mode fully implements all slave
C modes to be selected:
STOP Bit Detect
SSP BLOCK DIAGRAM
(I
SSPADD Reg
SSPBUF Reg
Match Detect
SSPSR Reg
START and
2
C MODE)
LSb
Write
(SSPSTAT Reg)
2
C operation:
Internal
Data Bus
Set, RESET
S, P Bits
Addr Match
2
C opera-
Selection of any I
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits.
Additional information on SSP I
found in the PICmicro™ Mid-Range MCU Reference
Manual (DS33023).
9.3.1
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
Either or both of the following conditions will cause the
SSP module not to give this ACK pulse.
a)
b)
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 9-2 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condi-
tion. Flag bit BF is cleared by reading the SSPBUF
register while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I
module are shown in timing parameter #100 and
parameter #101.
9.3.1.1
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condi-
tion, the eight bits are shifted into the SSPSR register.
All incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
b)
c)
d)
2
C specification, as well as the requirement of the SSP
The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
The SSPSR register value is loaded into the
SSPBUF register.
The buffer full bit, BF is set.
An ACK pulse is generated.
SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated, if enabled) - on the falling
edge of the ninth SCL pulse.
SLAVE MODE
Addressing
2
C mode, with the SSPEN bit set,
 2002 Microchip Technology Inc.
2
C operation may be