PIC16F72-I/SP Microchip Technology Inc., PIC16F72-I/SP Datasheet - Page 71

• Manufacturer Part Number: PIC16F72-I/SP
• Description: 28 PIN, 3.5 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F72-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

11.11.1
External interrupt on the RB0/INT pin is edge triggered,
either rising, if bit INTEDG (OPTION<6>) is set, or fall-
ing, if the INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit GIE decides whether or not the
processor branches to the interrupt vector following
wake-up. See Section 11.14 for details on SLEEP
mode.
11.11.2
An overflow (FFh → 00h) in the TMR0 register will set
flag bit TMR0IF (INTCON<2>). The interrupt can be
enabled/disabled
TMR0IE (INTCON<5>) (see Section 5.0).
EXAMPLE 11-1:
 2002 Microchip Technology Inc.
MOVWF
SWAPF
CLRF
MOVWF
:
:(ISR)
:
SWAPF
MOVWF
SWAPF
SWAPF
on
INT INTERRUPT
TMR0 INTERRUPT
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
the
by
RB0/INT
SAVING STATUS, W AND PCLATH REGISTERS IN RAM
setting/clearing
pin,
;Copy W to TEMP register
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Insert user code here
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
flag
enable
bit
INTF
bit
11.11.3
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>) (see
Section 3.2).
11.12 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt (i.e., W, STATUS registers).
This will have to be implemented in software, as shown
in Example 11-1.
For the PIC16F72 device, the register W_TEMP must
be defined in both banks 0 and 1 and must be defined
at the same offset from the bank base address (i.e., if
W_TEMP is defined at 20h in bank 0, it must also be
defined at A0h in bank 1). The register STATUS_TEMP
is only defined in bank 0.
PORTB INTCON CHANGE
PIC16F72
DS39597B-page 69