PIC16F872-I/SP Microchip Technology Inc., PIC16F872-I/SP Datasheet - Page 20

• Manufacturer Part Number: PIC16F872-I/SP
• Description: 28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F872-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F872
2.2.2.7
The PIR2 register contains the flag bits for the CCP2
interrupt, the SSP bus collision interrupt and the
EEPROM write operation interrupt.
.
REGISTER 2-7:
DS30221C-page 18
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-1
bit 0
PIR2 Register
PIR2 REGISTER (ADDRESS: 0Dh)
bit 7
Unimplemented: Read as '0'
Reserved: Always maintain this bit clear
Unimplemented: Read as '0'
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the SSP, when configured for I
0 = No bus collision has occurred
Unimplemented: Read as '0'
Reserved: Always maintain this bit clear
Legend:
R = Readable bit
- n = Value at POR
U-0
—
reserved
R/W-0
U-0
—
W = Writable bit
’1’ = Bit is set
R/W-0
EEIF
Note:
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R/W-0
BCLIF
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
© 2006 Microchip Technology Inc.
U-0
—
2
C Master mode
x = Bit is unknown
U-0
—
reserved
R/W-0
bit 0