PIC16F872-I/SP Microchip Technology Inc., PIC16F872-I/SP Datasheet - Page 67
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PIC16F872-I/SP
Manufacturer Part Number
PIC16F872-I/SP
Description
28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F872-ISP.pdf
(168 pages)
Specifications of PIC16F872-I/SP
A/d Inputs
5-Channel, 10-Bit
Cpu Speed
5 MIPS
Eeprom Memory
64 Bytes
Input Output
22
Interface
I2C/SPI
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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FIGURE 9-11:
9.2.9
To initiate a START condition, the user sets the START
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the baud rate genera-
tor is reloaded with the contents of SSPADD<6:0> and
starts its count. If SCL and SDA are both sampled high
when the baud rate generator times out (T
SDA pin is driven low. The action of the SDA being
driven low while SCL is high is the START condition,
and causes the S bit (SSPSTAT<3>) to be set. Follow-
ing this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (T
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware. The baud rate generator is suspended,
leaving the SDA line held low, and the START condition
is complete.
FIGURE 9-12:
© 2006 Microchip Technology Inc.
I
CONDITION TIMING
2
C MASTER MODE START
SDA
SCL
BRG
Value
BRG
Reload
Write to SEN bit occurs here
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
FIRST START BIT TIMING
03h
SDA
SCL
DX
SCL de-asserted but slave holds
SCL low (clock arbitration)
02h
SCL is sampled high, reload takes
place, and BRG starts its count.
BRG
BRG
SDA = 1,
SCL = 1
T
), the
), the
BRG
01h
Set S bit (SSPSTAT<3>)
T
S
BRG
BRG decrements
(on Q2 and Q4 cycles)
00h (hold off)
DX-1
At completion of START bit,
hardware clears SEN bit
9.2.9.1
If the user writes the SSPBUF when a START
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
and sets SSPIF bit
Note:
Note:
T
Write to SSPBUF occurs here
BRG
1st Bit
If, at the beginning of START condition, the
SDA and SCL pins are already sampled
low, or if during the START condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag (BCLIF) is
set, the START condition is aborted, and
the I
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
WCOL Status Flag
SCL allowed to transition high
T
2
03h
BRG
C module is reset into its IDLE state.
PIC16F872
02h
2nd Bit
DS30221C-page 65