PIC16F872-I/SP Microchip Technology Inc., PIC16F872-I/SP Datasheet - Page 49

• Manufacturer Part Number: PIC16F872-I/SP
• Description: 28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F872-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

8.2
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 8-2:
TABLE 8-2:
© 2006 Microchip Technology Inc.
0Bh,8Bh,
10Bh, 18Bh
0Ch
8Ch
87h
0Eh
0Fh
10h
15h
16h
17h
Legend:
Note 1: These bits are reserved; always maintain clear.
RC2/CCP1
Address
Special event trigger will:
Pin
Output Enable
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
TRISC<2>
Compare Mode
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.
INTCON
PIR1
PIE1
TRISC
TMR1L
TMR1H
T1CON
CCPR1L
CCPR1H
CCP1CON
Name
Q
Special Event Trigger
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
R
S
CCP1CON<3:0>
Mode Select
Output
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Logic
PORTC Data Direction Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
Bit 7
GIE
(1)
(1)
—
—
(PIR1<2>)
Set Flag bit CCP1IF
PEIE
ADIF
ADIE
Match
Bit 6
—
—
CCPR1H CCPR1L
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
TMR1H
TMR0IE
CCP1X
Comparator
Bit 5
(1)
(1)
TMR1L
CCP1Y
INTE
Bit 4
(1)
(1)
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
SSPIF
SSPIE
RBIE
Bit 3
8.2.1
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
8.2.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.2.3
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set, causing
a CCP interrupt (if enabled).
8.2.4
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled). This allows the CCPR1 regis-
ter to effectively be a 16-bit programmable period
register for Timer1.
Note:
Note:
TMR0IF
CCP1IF TMR2IF TMR1IF r0rr 0000 0000 0000
CCP1IE TMR2IE TMR1IE r0rr 0000 0000 0000
Bit 2
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the PORTC
I/O data latch.
The special event trigger from the CCP
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
CCP PIN CONFIGURATION
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
INTF
Bit 1
RBIF
Bit 0
PIC16F872
0000 000x 0000 000u
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Value on:
POR,
BOR
DS30221C-page 47
Value on
RESETS
all other