PIC18F1220-I/SO Microchip Technology Inc., PIC18F1220-I/SO Datasheet - Page 119

• Manufacturer Part Number: PIC18F1220-I/SO
• Description: Microcontroller; 4 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-SOIC
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F1220-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 4K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.3.4
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 15-1 shows the
FIGURE 15-1:
15.4
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 register
pair value, or the TMR3 register pair value. When a
match occurs, the RB3/CCP1/P1A pin:
• Is driven high
• Is driven low
• Toggles output (high-to-low or low-to-high)
• Remains unchanged (interrupt only)
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0. At the same time, interrupt
flag bit, CCP1IF, is set.
15.4.1
The user must configure the RB3/CCP1/P1A pin as an
output by clearing the TRISB<3> bit.
 2004 Microchip Technology Inc.
Note:
Compare Mode
CCP PRESCALER
CCP PIN CONFIGURATION
Clearing the CCP1CON register will force
the RB3/CCP1/P1A compare output latch
to the default low level. This is not the
PORTB I/O data latch.
CCP1 pin
CAPTURE MODE OPERATION BLOCK DIAGRAM
Q’s
Edge Detect
Prescaler
1, 4, 16
and
CCP1CON<3:0>
Set Flag bit CCP1IF
T3CCP1
T3CCP1
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 15-1:
15.4.2
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
15.4.3
When generate software interrupt is chosen, the RB3/
CCP1/P1A pin is not affected. CCP1IF is set and an
interrupt is generated (if enabled).
15.4.4
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special event trigger also sets the GO/DONE bit
(ADCON0<1>). This starts a conversion of the
currently selected A/D channel if the A/D is on.
CLRF
MOVLW
MOVWF
PIC18F1220/1320
CCP1CON
NEW_CAPT_PS
CCP1CON
TIMER1/TIMER3 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
TMR1
Enable
TMR3
Enable
CCPR1H
TMR1H
TMR3H
CHANGING BETWEEN
CAPTURE PRESCALERS
; Turn CCP module off
; Load WREG with the
; new prescaler mode
; value and CCP ON
; Load CCP1CON with
; this value
CCPR1L
TMR3L
TMR1L
DS39605C-page 117