PIC18F1220-I/SO Microchip Technology Inc., PIC18F1220-I/SO Datasheet - Page 45
PIC18F1220-I/SO
Manufacturer Part Number
PIC18F1220-I/SO
Description
Microcontroller; 4 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-SOIC
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F1220-ISO.pdf
(310 pages)
Specifications of PIC18F1220-I/SO
A/d Inputs
7-Channel, 10-Bit
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
16
Interface
USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin SOIC
Programmable Memory
4K Bytes
Ram Size
256 Bytes
Speed
20 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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REGISTER 5-1:
5.2.3
Since the Top-of-Stack (TOS) is readable and writable,
the ability to push values onto the stack and pull values
off the stack, without disturbing normal program execu-
tion, is a desirable option. To push the current PC value
onto the stack, a PUSH instruction can be executed.
This will increment the Stack Pointer and load the cur-
rent PC value onto the stack. TOSU, TOSH and TOSL
can then be modified to place data or a return address
on the stack.
The ability to pull the TOS value off of the stack and
replace it with the value that was previously pushed
onto the stack, without disturbing normal execution, is
achieved by using the POP instruction. The POP instruc-
tion discards the current TOS by decrementing the
Stack Pointer. The previous value pushed onto the
stack then becomes the TOS value.
2004 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4-0
PUSH AND POP INSTRUCTIONS
(1)
(1)
STKPTR REGISTER
bit 7
STKFUL: Stack Full Flag bit
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit
1 = Stack underflow occurred
0 = Stack underflow did not occur
Unimplemented: Read as ‘0’
SP4:SP0: Stack Pointer Location bits
Legend:
R = Readable bit
-n = Value at POR
STKFUL
R/C-0
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
STKUNF
R/C-0
W = Writable bit
‘1’ = Bit is set
U-0
—
R/W-0
SP4
5.2.4
These Resets are enabled by programming the STVR
bit in Configuration Register 4L. When the STVR bit is
cleared, a full or underflow condition will set the appro-
priate STKFUL or STKUNF bit, but not cause a device
Reset. When the STVR bit is set, a full or underflow
condition will set the appropriate STKFUL or STKUNF
bit and then cause a device Reset. The STKFUL or
STKUNF bits are cleared by the user software or a
Power-on Reset.
U = Unimplemented
‘0’ = Bit is cleared
PIC18F1220/1320
R/W-0
SP3
STACK FULL/UNDERFLOW RESETS
R/W-0
SP2
C = Clearable only bit
x = Bit is unknown
R/W-0
SP1
DS39605C-page 43
R/W-0
SP0
bit 0
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