PIC18F1220-I/SO Microchip Technology Inc., PIC18F1220-I/SO Datasheet - Page 54
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PIC18F1220-I/SO
Manufacturer Part Number
PIC18F1220-I/SO
Description
Microcontroller; 4 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-SOIC
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F1220-ISO.pdf
(310 pages)
Specifications of PIC18F1220-I/SO
A/d Inputs
7-Channel, 10-Bit
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
16
Interface
USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin SOIC
Programmable Memory
4K Bytes
Ram Size
256 Bytes
Speed
20 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC18F1220/1320
5.10
The Access Bank is an architectural enhancement
which is very useful for C compiler code optimization.
The techniques used by the C compiler may also be
useful for programs written in assembly.
This data memory region can be used for:
• Intermediate computational values
• Local variables of subroutines
• Faster context saving/switching of variables
• Common variables
• Faster evaluation/control of SFRs (no banking)
The Access Bank is comprised of the last 128 bytes in
Bank 15 (SFRs) and the first 128 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 5-6
indicates the Access RAM areas.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
the Access Bank. This bit is denoted as the ‘a’ bit (for
access bit).
When forced in the Access Bank (a = 0), the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function Registers, so these registers can
be accessed without any software overhead. This is
useful for testing status flags and modifying control bits.
FIGURE 5-7:
DS39605C-page 52
Note 1: For register file map detail, see Table 5-1.
Bank Select
0
BSR<7:4>
Access Bank
0 0
2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers
3: The MOVFF instruction embeds the entire 12-bit address in the instruction.
of the Access Bank.
(2)
0
DIRECT ADDRESSING
BSR<3:0>
Location Select
7
Data
Memory
From Opcode
(1)
(3)
Direct Addressing
(3)
000h
0FFh
Bank 0
5.11
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into as many as sixteen banks. When using
direct addressing, the BSR should be configured for the
desired bank.
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ‘0’s and
writes will have no effect (see Figure 5-7).
A MOVLB instruction has been provided in the instruction
set to assist in selecting banks.
If the currently selected bank is not implemented, any
read will return all ‘0’s and all writes are ignored. The
Status register bits will be set/cleared as appropriate for
the instruction performed.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A MOVFF instruction ignores the BSR, since the 12-bit
addresses are embedded into the instruction word.
Section 5.12 “Indirect Addressing, INDF and FSR
Registers” provides a description of indirect address-
ing, which allows linear addressing of the entire RAM
space.
00h
0
100h
1FFh
Bank Select Register (BSR)
Bank 1
01h
2004 Microchip Technology Inc.
E00h
EFFh
Bank 14
0Eh
F00h
FFFh
Bank 15
0Fh
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