PIC18F1220-I/SO Microchip Technology Inc., PIC18F1220-I/SO Datasheet - Page 155
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F1220-I/SO
Manufacturer Part Number
PIC18F1220-I/SO
Description
Microcontroller; 4 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-SOIC
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F1220-ISO.pdf
(310 pages)
Specifications of PIC18F1220-I/SO
A/d Inputs
7-Channel, 10-Bit
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
16
Interface
USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin SOIC
Programmable Memory
4K Bytes
Ram Size
256 Bytes
Speed
20 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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16.5.2
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep, or any
Idle mode and bit SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG register; if the RCIE enable bit is set, the inter-
rupt generated will wake the chip from low-power
mode. If the global interrupt is enabled, the program will
branch to the interrupt vector.
TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
2004 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCTL
SPBRGH
SPBRG
Legend: x = unknown,
Name
EUSART Receive Register
Baud Rate Generator Register High Byte
Baud Rate Generator Register Low Byte
EUSART SYNCHRONOUS SLAVE
RECEPTION
GIE/GIEH
CSRC
SPEN
Bit 7
—
—
—
—
–
PEIE/GIEL
= unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
TMR0IE
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
—
INT0IE
CREN
SYNC
SCKP
TXIE
TXIP
Bit 4
TXIF
ADDEN
SENDB
BRG16
RBIE
Bit 3
—
—
—
To set up a Synchronous Slave Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
TMR0IF
CCP1IF
CCP1IE
CCP1IP
BRGH
FERR
Bit 2
—
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit, RCIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCIE, was set.
Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
PIC18F1220/1320
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
WUE
Bit 1
TMR1IF
TMR1IE
TMR1IP
ABDEN
RX9D
TX9D
RBIF
Bit 0
0000 000x
-000 -000
-000 -000
-111 -111
0000 000x
0000 0000
0000 0010
-1-1 0-00
0000 0000
0000 0000
POR, BOR
Value on
DS39605C-page 153
0000 000u
-000 -000
-000 -000
-111 -111
0000 000x
0000 0000
0000 0010
-1-1 0-00
0000 0000
0000 0000
Value on
all other
Resets
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