PIC18F1220-I/SO Microchip Technology Inc., PIC18F1220-I/SO Datasheet - Page 146
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F1220-I/SO
Manufacturer Part Number
PIC18F1220-I/SO
Description
Microcontroller; 4 KB Flash; 256 RAM; 256 EEPROM; 16 I/O; 18-Pin-SOIC
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F1220-ISO.pdf
(310 pages)
Specifications of PIC18F1220-I/SO
A/d Inputs
7-Channel, 10-Bit
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
16
Interface
USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin SOIC
Programmable Memory
4K Bytes
Ram Size
256 Bytes
Speed
20 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC18F1220/1320
To set up an Asynchronous Transmission:
1.
2.
3.
4.
FIGURE 16-6:
TABLE 16-6:
DS39605C-page 144
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCTL
SPBRGH
SPBRG
Legend:
Name
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (see Section 16.2 “EUSART
Baud Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
Note:
RX (pin)
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
EUSART Receive Register
Baud Rate Generator Register High Byte
Baud Rate Generator Register Low Byte
GIE/GIEH
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after
the third word, causing the OERR (overrun) bit to be set.
SPEN
CSRC
Bit 7
—
—
—
—
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Start
bit
ASYNCHRONOUS RECEPTION
PEIE/GIEL
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit 0
bit 1
TMR0IE
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
—
bit 7/8
INT0IE
CREN
SYNC
SCKP
TXIE
TXIP
Bit 4
TXIF
Stop
bit
ADDEN
SENDB
BRG16
Word 1
RCREG
RBIE
Bit 3
Start
—
—
—
bit
bit 0
TMR0IF
CCP1IF TMR2IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
5.
6.
7.
If using interrupts, ensure that the GIE and PEIE bits in
the INTCON register (INTCON<7:6>) are set.
BRGH
FERR
Bit 2
—
Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts
transmission).
INT0IF
OERR
TRMT
WUE
bit 7/8
Bit 1
Word 2
RCREG
Stop
bit
TMR1IF
ABDEN
RX9D
TX9D
RBIF
Bit 0
Start
bit
2004 Microchip Technology Inc.
0000 000x
-000 -000
-000 -000
-111 -111
0000 000x
0000 0000
0000 0010
-1-1 0-00
0000 0000
0000 0000
POR, BOR
Value on
bit 7/8
Stop
bit
0000 000u
-000 -000
-000 -000
-111 -111
0000 000x
0000 0000
0000 0010
-1-1 0-00
0000 0000
0000 0000
Value on
all other
Resets
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