ICS1893CF IDT, Integrated Device Technology Inc, ICS1893CF Datasheet - Page 51

• Manufacturer Part Number: ICS1893CF
• Description: PHYCEIVER LOW PWR 3.3V 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893CF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Other names: 1893CF

7.3.2 100Base-TX Full Duplex (bit 1.14)
7.3.3 100Base-TX Half Duplex (bit 1.13)
7.3.4 10Base-T Full Duplex (bit 1.12)
7.3.5 10Base-T Half Duplex (bit 1.11)
ICS1893CF, Rev. K, 05/13/10
The STA reads this bit to learn if the ICS1893CF can support 100Base-TX, full-duplex operations. The
ISO/IEC specification requires that the ICS1893CF must set bit 1.14 to logic:
•
•
Bit 1.14 is a Command Override Write bit, which allows an STA to alter the default value of this bit. [See the
description of bit 16.15, the Command Override Write Enable bit, in
Control
The STA reads this bit to learn if the ICS1893CF can support 100Base-TX, half-duplex operations. The
ISO/IEC specification requires that the ICS1893CF must set bit 1.13 to logic:
•
•
This bit 1.13 is a Command Override Write bit, which allows an STA to alter the default value of this bit.
[See the description of bit 16.15, the Command Override Write Enable bit, in
Extended Control
The STA reads this bit to learn if the ICS1893CF can support 10Base-T, full-duplex operations. The
ISO/IEC specification requires that the ICS1893CF must set bit 1.12 to logic:
•
•
This bit 1.12 is a Command Override Write bit, which allows an STA to alter the default value of this bit.
[See the description of bit 16.15, the Command Override Write Enable bit, in
Extended Control
The STA reads this bit to learn if the ICS1893CF can support 10Base-T, half-duplex operations. The
ISO/IEC specification requires that the ICS1893CF must set bit 1.11 to logic:
•
•
Bit 1.11 of the ICS1893CF Status Register is a Command Override Write bit., which allows an STA to alter
the default value of this bit. [See the description of bit 16.15, the Command Override Write Enable bit, in
Section 7.11, “Register 16: Extended Control
Zero if it cannot support 100Base-TX, full-duplex operations.
One if it can support 100Base-TX, full-duplex operations. (For the ICS1893CF, the default value of bit
1.14 is logic one, in that the ICS1893CF supports 100Base-TX, full-duplex operations.)
Zero if it cannot support 100Base-TX, half-duplex operations.
One if it can support 100Base-TX, half-duplex operations. (For the ICS1893CF, the default value of bit
1.13 is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the
ICS1893CF supports 100Base-TX, half-duplex operations.)
Zero if it cannot support 10Base-T, full-duplex operations.
One if it can support 10Base-T, full-duplex operations. (For the ICS1893CF, the default value of bit 1.12
is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the ICS1893CF
supports 10Base-T, full-duplex operations.)
Zero if it cannot support 10Base-T, half-duplex operations.
One if it can support 10Base-T, half-duplex operations. (For the ICS1893CF, the default value of bit 1.11
is logic one. Therefore, when an STA reads the Status Register, the STA is informed that the ICS1893CF
supports 10Base-T, half-duplex operations.)
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ICS1893CF Data Sheet Rev. J - Release
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Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
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51
Section 7.11, “Register 16: Extended
Chapter 7 Management Register Set
Section 7.11, “Register 16:
Section 7.11, “Register 16:
May, 2010