ICS1893CF IDT, Integrated Device Technology Inc, ICS1893CF Datasheet - Page 56

• Manufacturer Part Number: ICS1893CF
• Description: PHYCEIVER LOW PWR 3.3V 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893CF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Other names: 1893CF

IEEE-Assigned Organizationally Unique Identifier (OUI)
7.5 Register 3: PHY Identifier Register
ICS1893CF, Rev. K, 05/13/10
For each manufacturing organization, the IEEE assigns an 3-octet OUI. For Integrated Circuit Systems,
Inc. the IEEE-assigned 3-octet OUI is 00A0BEh. This OUI is retained for backwards compatibility with older
versions of the ICS1893.
The binary representation of an OUI is formed by expressing each octet as a sequence of eight bits, from
least significant to most significant, and from left to right.
of the OUI (in IEEE Std. 802-1990 format) to Management Registers 2 and 3.
Table 7-8. IEEE-Assigned Organizationally Unique Identifier
Table 7-9
that are part of a set defined by the ISO/IEC specification. This register stores the following:
•
•
•
All the bits in the two PHY Identifier Registers are Command Override Write bits. An STA can read them at
any time without condition. However, An STA can modify these register bits only when the Command
Register Override bit (bit 16.15) is enabled with a logic one.
Note:
Table 7-9. PHY Identifier Register (Register 3 [0x03])
a
1
0
3.15
3.14
3.13
3.12
Part of the OUI [see the text in
Manufacturer’s PHY Model Number
Manufacturer’s PHY Revision Number
Bit
b
2
0
0
For an explanation of acronyms used in
OUI bit 19 | s
OUI bit 20 | t
OUI bit 21 | u
OUI bit 22 | v
ICS1893CF Data Sheet - Release
lists the bits for PHY Identifier Register (Register 3), which is one of two PHY Identifier Registers
c
3
0
First Octet
2.15:12
d
4
0
0
e
5
0
Definition
6
0
f
0
g
7
0
Copyright © 2009, Integrated Device Technology, Inc.
2.11:8
h
8
0
Section 7.4, “Register 2: PHY Identifier
0
9
0
i
Register 2
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
0
j
When Bit = 0 When Bit = 1
0
All rights reserved.
Second Octet
k
0
N/A
N/A
N/A
N/A
56
Table
0
l
2.7:4
1
m
0
7-5, see
Table 7-8
n
1
A
N/A
N/A
N/A
N/A
o
0
Chapter 1, “Abbreviations and
provides the ISO/IEC-defined mapping
p
1
2.3:0
5
Access
Chapter 7 Management Register Set
q
0
CW
CW
CW
CW
Register”]
1
r
E
1
s
Function
Special
Third Octet
3.15:12
–
–
–
–
1
t
F
Register 3
u
1
Default
1
Acronyms”.
v
1
1
1
1
B
May, 2010
3.11:10
w
0
1
Hex
F
x
1