ICS1893CF IDT, Integrated Device Technology Inc, ICS1893CF Datasheet - Page 73

• Manufacturer Part Number: ICS1893CF
• Description: PHYCEIVER LOW PWR 3.3V 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893CF

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Other names: 1893CF

7.12.1 Data Rate (bit 17.15)
7.12.2 Duplex (bit 17.14)
7.12.3 Auto-Negotiation Progress Monitor (bits 17.13:11)
ICS1893CF, Rev. K, 05/13/10
The Data Rate bit indicates the ‘selected technology’. If the ICS1893CF is in:
•
•
When bit 17.15 is logic:
•
•
Note:
The Duplex bit indicates the ‘selected technology’. If the ICS1893CF is in:
•
•
When bit 17.14 is logic:
•
•
Note:
The Auto-Negotiation Progress Monitor consists of the Auto-Negotiation Complete bit (bit 17.4) and the
three Auto-Negotiation Monitor bits (bits 17.13:11). The Auto-Negotiation Progress Monitor continually
examines the state of the Auto-Negotiation Process State Machine and reports the status of
Auto-Negotiation using the three Auto-Negotiation Monitor bits. Therefore, the value of these three bits
provides the status of the Auto-Negotiation Process.
These three bits are initialized to logic zero in one of the following ways:
•
•
•
If Auto-Negotiation is enabled, these bits continually latch the highest state that the Auto-Negotiation State
Machine achieves. That is, they are updated only if the binary value of the next state is greater than the
binary value of the present state as outlined in
Hardware mode, the value of this bit is determined by the 10/100SEL input pin.
Software mode, the value of this bit is determined by the Data Rate bit 0.13.
Zero, it indicates that 10-MHz operations are selected.
One, the ICS1893CF is indicating that 100-MHz operations are selected.
Hardware mode, the value of this bit is determined by the DPXSEL input pin.
Software mode, the value of this bit is determined by the Duplex Mode bit 0.8.
Zero, it indicates that half-duplex operations are selected.
One, the ICS1893CF is indicating that full-duplex operations are selected.
A reset (see
Disabling Auto-Negotiation [see
Restarting Auto-Negotiation [see
ICS1893CF Data Sheet Rev. J - Release
This bit does not imply any link status.
This bit does not imply any link status.
Section 4.1, “Reset
Copyright © 2009, Integrated Device Technology, Inc.
Section 7.2.4, “Auto-Negotiation Enable (bit
Operations”)
Section 7.2.7, “Restart Auto-Negotiation (bit
All rights reserved.
Table
73
7-19.
Chapter 7 Management Register Set
0.12)”]
0.9)”]
May, 2010