IDT82V2041EPP IDT, Integrated Device Technology Inc, IDT82V2041EPP Datasheet - Page 20

• Manufacturer Part Number: IDT82V2041EPP
• Description: IC LIU T1/J1/E1 1CH 44-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Line Interface Units (LIUs)r

Specifications of IDT82V2041EPP

• Protocol: E1
• Voltage - Supply: 3.13 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82V2041EPP

3.3.4
impedance matching can be realized by the internal impedance matching
circuit or the external impedance matching circuit. If T_TERM[2] is set to
‘0’, the internal impedance matching circuit will be selected. In this case,
the T_TERM[1:0] bits (TERM, 03H) can be set to choose 75 Ω, 100 Ω, 110
Ω or 120 Ω internal impedance of TTIP/TRING. If T_TERM[2] is set to ‘1’,
the internal impedance matching circuit will be disabled. In this case, the
external impedance matching circuit will be used to realize the impedance
matching. For T1/J1 mode, the external impedance matching circuit for the
transmitter is not supported.
ponents to connect with the cable.
impedance matching for transmitter.
matching for both receiver and transmitter. If TERM pin is low, external
impedance network will be used for impedance matching. If TERM pin is
high, internal impedance will be used for impedance matching and
Table-10 Impedance Matching for Transmitter
3.3.5
05H) to ‘1’. In this case, the TTIP/TRING pins are turned into high imped-
ance.
Functional Description
IDT82V2041E
The transmit line interface consists of TTIP pin and TRING pin. The
In hardware control mode, TERM pin can be used to select impedance
Note: The precision of the resistors should be better than ± 1%
The transmit path can be powered down by setting the T_OFF bit (TCF0,
Cable Configuration
TRANSMIT PATH LINE INTERFACE
TRANSMIT PATH POWER DOWN
T1/133~266 ft
T1/266~399 ft
T1/399~533 ft
T1/533~655 ft
T1/0~133 ft
J1/0~655 ft
E1/120 Ω
E1/75 Ω
Figure-8
Table-10
shows the appropriate external com-
T_TERM[2:0]
000
001
010
011
is the list of the recommended
Internal Termination
PULS[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
20
PULS[3:0] pins will be set to select the specific internal impedance. Refer
to
the THZ bit (TCF1, 06H) to ‘1’. In this state, the internal transmit circuits are
still active.
ance by pulling THZ pin to high. Refer to
for details.
high impedance:
•
•
•
•
pulling both PATT1 and PATT0 pins to high. Refer to
Pin Summary
0 Ω
R
5 Hardware Control Pin Summary
The TTIP/TRING pins can also be turned into high impedance by setting
In hardware control mode, TTIP/TRING can be turned into high imped-
Besides, in the following cases, both TTIP/TRING pins will also become
In hardware control mode, the transmit path can be powered down by
T
Loss of MCLK;
Loss of TCLK (exceptions: Remote Loopback; Transmit internal
pattern by MCLK);
Transmit path power down;
After software reset; pin reset and power on.
for details.
T_TERM[2:0]
1XX
-
External Termination
for details.
PULS[3:0]
5 Hardware Control Pin Summary
0001
0001
-
December 9, 2005
5 Hardware Control
9.4 Ω
R
-
T