IDT82V2041EPP IDT, Integrated Device Technology Inc, IDT82V2041EPP Datasheet - Page 34

• Manufacturer Part Number: IDT82V2041EPP
• Description: IC LIU T1/J1/E1 1CH 44-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Line Interface Units (LIUs)r

Specifications of IDT82V2041EPP

• Protocol: E1
• Voltage - Supply: 3.13 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82V2041EPP

3.11 MCLK AND TCLK
3.11.1 MASTER CLOCK (MCLK)
MHz for T1/J1 applications and 2.048 MHz in E1 mode. This reference clock
is used to generate several internal reference signals:
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MCLK and TCLK. The missing of MCLK will set the TTIP/TRING to high
impedance state.
Functional Description
IDT82V2041E
MCLK is an independent, free-running reference clock. MCLK is 1.544
Figure-18
Timing reference for the integrated clock recovery unit.
Timing reference for the integrated digital jitter attenuator.
Timing reference for microcontroller interface.
Generation of RCLK signal during a loss of signal condition if AIS is
enabled.
Reference clock during Transmit All Ones, All Zeros, PRBS/QRSS
pattern and Inband Loopback code if it is selected as the reference
clock. For ATAO and AIS, MCLK is always used as the reference
clock.
Reference clock during Transmit All Ones (TAO) condition or send-
ing PRBS/QRSS in hardware
shows the chip operation status in different conditions of
transmitter high impedance
MCLK=H/L?
control
mode.
yes
Figure-18 TCLK Operation Flowchart
generate transmit clock loss
interrupt if not masked in
software control mode;
transmitter high impedance
Clocked
SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
34
3.11.2 TRANSMIT CLOCK (TCLK)
active edge of TCLK can be selected by the TCLK_SEL bit (TCF0, 05H).
During Transmit All Ones, PRBS/QRSS patterns or Inband Loopback
Code, either TCLK or MCLK can be used as the reference clock. This is
selected by the PATT_CLK bit (MAINT0, 0DH).
reference clock and the PATT_CLK bit is ignored. In Automatic Transmit
All Ones condition, the ATAO bit (MAINT0, 0DH) is set to ‘1’. In AIS condi-
tion, the AISE bit (MAINT0, 0DH) is set to ‘1’.
bit (STAT0, 17H) will be set, and the TTIP/TRING will become high imped-
ance if the chip is not used for remote loopback or is not using MCLK to trans-
mit internal patterns (TAOS, All Zeros, PRBS and in-band loopback code).
When TCLK is detected again, TCLK_LOS bit (STAT0, 17H) will be cleared.
The reference frequency to detect a TCLK loss is derived from MCLK.
L/H
TCLK is used to sample the transmit data on TD/TDP and TDN. The
But for Automatic Transmit All Ones and AIS, only MCLK is used as the
If TCLK has been missing for more than 70 MCLK cycles, TCLK_LOS
TCLK status?
normal operation
clocked
December 9, 2005