IDT82V2041EPP IDT, Integrated Device Technology Inc, IDT82V2041EPP Datasheet - Page 63
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IDT82V2041EPP
Manufacturer Part Number
IDT82V2041EPP
Description
IC LIU T1/J1/E1 1CH 44-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Line Interface Units (LIUs)r
Datasheet
1.IDT82V2041EPP8.pdf
(75 pages)
Specifications of IDT82V2041EPP
Protocol
E1
Voltage - Supply
3.13 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Number Of Transceivers
1
Screening Level
Industrial
Mounting
Surface Mount
Package Type
TQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Drivers/receivers
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
82V2041EPP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82V2041EPP
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT82V2041EPP8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT82V2041EPPG
Manufacturer:
IDT
Quantity:
351
Company:
Part Number:
IDT82V2041EPPG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT82V2041EPPG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Table-58 Transmitter and Receiver Timing Characteristics
1.Relative to nominal frequency, MCLK= ± 100 ppm
2.RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK duty cycles are for worst case jitter conditions (0.2 UI displacement
3.For all digital outputs. C load = 15 pF
Transmit path
t1
t2
Receive path
t4
t5
t6
t7
t8
Test Specifications
IDT82V2041E
for E1 per ITU G.823).
Symbol
MCLK frequency
E1:
T1/J1:
MCLK tolerance
MCLK duty cycle
TCLK frequency
E1:
T1/J1:
TCLK tolerance
TCLK Duty Cycle
Transmit Data Setup Time
Transmit Data Hold Time
Delay time of THZ low to driver high impedance
Delay time of TCLK low to driver high impedance
Clock recovery capture range
RCLK duty cycle
RCLK pulse width
E1:
T1/J1:
RCLK pulse width low time
E1:
T1/J1:
RCLK pulse width high time
E1:
T1/J1:
Rise/fall time
Receive Data Setup Time
E1:
T1/J1:
Receive Data Hold Time
E1:
T1/J1:
3
2
2
Parameter
1
E1
T1/J1
SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
63
-100
Min
457
607
203
259
203
259
200
200
200
200
-50
30
10
40
40
40
± 180
2.048
1.544
2.048
1.544
± 80
Typ
488
648
244
324
244
324
244
324
244
324
75
50
Max
100
+50
519
689
285
389
285
389
70
90
10
60
20
December 9, 2005
MHz
MHz
Unit
ppm
ppm
ppm
U.I.
ns
ns
us
ns
ns
ns
ns
ns
ns
%
%
%