IDT82V2084PF IDT, Integrated Device Technology Inc, IDT82V2084PF Datasheet - Page 12

• Manufacturer Part Number: IDT82V2084PF
• Description: IC LIU T1/J1/E1 4CH 128-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Line Interface Units (LIUs)r

Specifications of IDT82V2084PF

• Protocol: E1
• Voltage - Supply: 3.13 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82V2084PF

QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
SCLKE
GNDIO
VDDT1
VDDT2
VDDT3
VDDT4
GNDT1
GNDT2
GNDT3
GNDT4
VDDR1
VDDR2
VDDR3
VDDR4
VDDIO
GNDA
GNDD
VDDA
VDDD
Name
TRST
TMS
TCK
TDO
THZ
REF
TDI
Tri-state
Output
Pullup
Pullup
Pullup
Input
Input
Input
Input
Input
Input
Input
Type
-
-
-
-
-
-
-
-
-
TQFP128
101, 102
105, 106
111, 112
115, 116
44, 121 3.3V Analog Core Power Supply
41, 122 Core Analog Ground
13, 22
68, 81
12, 23
69, 83
45, 46
55, 56
49, 50
59, 60
11, 84
9, 85
123
124
127
126
125
120
110
43
99
98
54
64
4
5
THZ: Transmit Driver Enable
This pin enables or disables all transmitter drivers on a global basis. A low level on this pin enables the drivers while a high level
turns all drivers into high impedance state. Note that functionality of internal circuits is not affected by signal on this pin.
REF: Reference Resistor
An external resistor (3 KΩ, 1%) is used to connect this pin to ground to provide a standard reference current for internal circuit.
SCLKE: Serial Clock Edge Select
Signal on this pin determines the active edge of SCLK to output SDO. The active clock edge is selected as shown below:
TRST: JTAG Test Port Reset
This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pull-up resistor. To ensure deterministic
operation of the test logic, TMS should be held high while the signal applied to TRST changes from low to high.
For normal signal processing, this pin should be connected to ground.
TMS: JTAG Test Mode Select
This pin is used to control the test logic state machine and is sampled on the rising edges of TCK. TMS has an internal pull-up
resistor.
TCK: JTAG Test Clock
This pin is the input clock for JTAG. The data on TDI and TMS is clocked into the device on the rising edges of TCK while the
data on TDO is clocked out of the device on the falling edges of TCK. When TCK is idle at a low level, all stored-state devices
contained in the test logic will retain their state indefinitely.
TDO: JTAG Test Data Output
This is a tri-state output signal and used for reading all the serial configuration and test data from the test logic. The data on TDO
is clocked out of the device on the falling edges of TCK.
TDI: JTAG Test Data Input
This pin is used for loading instructions and data into the test logic and has an internal pullup resistor. The data on TDI is clocked
into the device on the rising edges of TCK.
3.3V I/O Power Supply
I/O Ground
3.3V Power Supply for Transmitter Driver
Analog Ground for Transmitter Driver
3.3V Digital Core Power Supply
Core Digital Ground
3.3V Power Supply for Receiver
SCLKE
High
Low
Power Supplies and Grounds
Rising edge is active edge
Falling edge is active edge
JTAG Signals
12
SCLK
Description
TEMPERATURE RANGES
INDUSTRIAL