PEB3086FV14XT Lantiq, PEB3086FV14XT Datasheet - Page 100

• Manufacturer Part Number: PEB3086FV14XT
• Manufacturer: Lantiq

Specifications of PEB3086FV14XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

ISAC-SX
PEB 3086
Description of Functional Blocks
Figure 51
shows the timing of looping TSa from DU to DD (a = 0...11) via CDAxy
register. TSa is read in the CDAxy register from DU and is written one frame later on DD.
.
a = 0...11
FSC
DU
TSa
TSa
CDAxy
*)
µC
DD
TSa
TSa
*) if access by the µC is required
Figure 51
Data Access when Looping TSa from DU to DD
Figure 52
shows the timing of shifting data from TSa to TSb on DU (DD). In
Figure 52a)
shifting is done in one frame because TSa and TSb didn’t succeed direct one another (a,
b = 0...9 and b ³ a+2 . In
Figure 52b)
shifting is done from one frame to the following
frame. This is the case when the time slots succeed one other (b = a+1) or b is smaller
than a (b < a).
At looping and shifting the data can be accessed by the controller between the
synchronous transfer interrupt (STI) and the status overflow interrupt (STOV). STI and
STOV are explained in the section ’Synchronous Transfer’. If there is no controller
intervention the looping and shifting is done autonomous.
Data Sheet
100
2003-01-30