PEB3086FV14XT Lantiq, PEB3086FV14XT Datasheet - Page 166

• Manufacturer Part Number: PEB3086FV14XT
• Manufacturer: Lantiq

Specifications of PEB3086FV14XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

ISAC-SX
PEB 3086
Detailed Register Description
If an XMR interrupt occurs the transmit FIFO is locked until the XMR interrupt is read by
the host (interrupt cannot be read if masked in MASKD).
XDU ... Transmit Data Underrun
The current transmission of a frame is aborted by transmitting seven ’1’s because the
XFIFOD holds no further data. This interrupt occurs whenever the microcontroller has
failed to respond to an XPR interrupt (ISTAD register) quickly enough, after having
initiated a transmission and the message to be transmitted is not yet complete.
If an XDU interrupt occurs the transmit FIFO is locked until the XDU interrupt is read by
the host (interrupt cannot be read if masked in MASKD).
4.1.4
MASKD - Mask Register D-Channel
Value after reset: FF
H
7
0
MASKD
RME
RPF
RFO
XPR
XMR
XDU
1
1
WR (20)
Each interrupt source in the ISTAD register can selectively be masked by setting the
corresponding bit in MASKD to ’1’. Masked interrupt status bits are not indicated when
ISTAD is read. Instead, they remain internally stored and pending until the mask bit is
reset to ’0’.
Data Sheet
166
2003-01-30