PEB3086FV14XT Lantiq, PEB3086FV14XT Datasheet - Page 131

• Manufacturer Part Number: PEB3086FV14XT
• Manufacturer: Lantiq

Specifications of PEB3086FV14XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

After the clocks have been enabled this is indicated by the PU code in the C/I channel
and, consequently, by a CIC interrupt. The DU line may be released by resetting the
Software Power Up bit IOM_CR =’0’ and the C/I code written to CIX0 before (e.g. TIM or
AR8) is output on DU.
The ISAC-SX supplies IOM-2 timing signals as long as there is no DIU command in the
C/I (C/I0) channel. If timing signals are no longer required and activation is not yet
requested, this is indicated by programming DIU in the CIX0 register.
Figure 71
Data Sheet
FSC
DU
DD
FSC
DU
DD
DCL
SPU = 1
Activation of the IOM-2 interface
0.2 to 4 ms
Note: The value “132 x DCL” is only valid for
IOM configurations with 3 IOM channels.
MR
MX
IOM -CH1
IOM
132 x DCL
R
R
-CH1
131
PU
IOM -CH2
IOM -CH2
R
R
Description of Functional Blocks
CIC : CIXO = TIM
Int.
PU
SPU = 0
B1
B1
TIM
PU
ITD09656
TIM
PU
TIM
PU
PEB 3086
2003-01-30
ISAC-SX