PEB3086FV14XT Lantiq, PEB3086FV14XT Datasheet - Page 42

• Manufacturer Part Number: PEB3086FV14XT
• Manufacturer: Lantiq

Specifications of PEB3086FV14XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 6
RSS2
Bit 1
0
0
1
1
• C/I Code Change (Exchange Awake)
• EAW (Subscriber Awake)
• Watchdog Timer
After the selection of the watchdog timer (RSS = ’11’) an internal timer is reset and
started. During every time period of 128 ms the microcontroller has to program the
WTC1- and WTC2 bits in the following sequence to reset and restart the watchdog timer:
If not, the timer expires and a WOV-interrupt (ISTA Register) together with a reset pulse
of 125 µs is generated.
Deactivation of the watchdog timer is only possible with a hardware reset.
External Reset Input
At the RES input an external reset can be applied forcing the device in the reset state.
This external reset signal is additionally fed to the RSTO output. The length of the reset
signal is specified in
After an external reset from the RES pin all registers of the device are set to its reset
values (see register description in
Software Reset Register (SRES)
Every main functional block of the device can be reset separately by software setting the
corresponding bit in the SRES register. A reset to external devices can also be controlled
in this way. The reset state is activated by setting the corresponding bit to ’1’ and onchip
Data Sheet
A change in the downstream C/I channel (C/I0) generates an external reset pulse of
125 µs £ t £ 250 µs.
A low level on the EAW input starts the oscillator from the power down state and
generates a reset pulse of 125 µs £ t £ 250 µs.
RSS1
Bit 0
0
1
0
1
Reset Source Selection
1.
2.
Chapter
C/I Code
Change
--
x
--
WTC1
1
0
5.9.
Chapter
WTC2
0
1
42
4).
EAW
--
x
--
reserved
Description of Functional Blocks
Watchdog
Timer
--
--
x
PEB 3086
2003-01-30
ISAC-SX