PIC18F6585-I/PT Microchip Technology Inc., PIC18F6585-I/PT Datasheet - Page 131

• Manufacturer Part Number: PIC18F6585-I/PT
• Description: 64 PIN, 48 KB FLASH, 3328 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6585-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 48K Bytes
• Ram Size: 3.3K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 10-6:
FIGURE 10-7:
 2004 Microchip Technology Inc.
Note 1:
Note 1:
2:
3:
2:
I/O pin has diode protection to V
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
For PIC18FXX85 parts, the CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0) in the Configuration
register and the device is operating in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller mode.
I/O pins have diode protection to V
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
RBPU
Data Bus
RD TRISB
RD LATB
RD PORTB
BLOCK DIAGRAM OF RB2:RB0 PINS
BLOCK DIAGRAM OF RB3 PIN
CCP2MX
CCP Output
Enable
CCP Output
WR LATB or
WR PORTB
WR TRISB
RD PORTB
CCP2 or INT3
(2)
(3)
(3)
Data Bus
INTx
RBPU
WR Port
WR TRIS
RD TRIS
RD Port
Schmitt Trigger
Buffer
(2)
DD
TRIS Latch
Data Latch
D
D
and V
CK
CK
DD
and V
SS
PIC18F6585/8585/6680/8680
Q
Q
.
Data Latch
TRIS Latch
CCP2MX = 0
D
D
CK
CK
SS
.
Schmitt Trigger
Buffer
Q
Q
Q
1
0
EN
D
Q
EN
TTL
Input
Buffer
D
V
P
RD Port
DD
Weak
Pull-up
V
I/O pin
V
N
P
SS
DD
(1)
TTL
Input
Buffer
V
P
DD
Weak
Pull-up
I/O pin
(1)
DS30491C-page 129