PIC18F6585-I/PT Microchip Technology Inc., PIC18F6585-I/PT Datasheet - Page 334

• Manufacturer Part Number: PIC18F6585-I/PT
• Description: 64 PIN, 48 KB FLASH, 3328 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6585-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 48K Bytes
• Ram Size: 3.3K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F6585/8585/6680/8680
23.6.2
The MCU can request to abort a message by clearing
the TXREQ bit associated with the corresponding mes-
sage buffer (TXBnCON<3> or BnCON<3>). Setting the
ABAT bit (CANCON<4>) will request an abort of all
pending messages. If the message has not yet started
transmission or if the message started but is inter-
rupted by loss of arbitration or an error, the abort will be
processed. The abort is indicated when the module
sets the TXABT bit for the corresponding buffer
(TXBnCON<6> or BnCON<6>). If the message has
started to transmit, it will attempt to transmit the current
message fully. If the current message is transmitted
fully and is not lost to arbitration or an error, the TXABT
bit will not be set because the message was transmit-
ted successfully. Likewise, if a message is being
transmitted during an abort request and the message is
lost to arbitration or an error, the message will not be
retransmitted and the TXABT bit will be set, indicating
that the message was successfully aborted.
FIGURE 23-2:
DS30491C-page 332
Message
Control
ABORTING TRANSMISSION
Queue
TXB0
TRANSMIT BUFFERS
TXB1
Transmit Byte Sequencer
Once an abort is requested by setting ABAT or TXABT
bits, it cannot be cleared to cancel the abort request.
Only CAN module hardware or a POR condition can
clear it.
23.6.3
Transmit
PIC18F6585/8585/6680/8680 devices of the pending
transmittable messages. This is independent from and
not related to any prioritization implicit in the message
arbitration scheme built into the CAN protocol. Prior to
sending the SOF, the priority of all buffers that are
queued for transmission is compared. The transmit
buffer with the highest priority will be sent first. If more
than one buffer has the same priority setting, the mes-
sage is transmitted in the order of TXB2, TXB1, TXB0,
B5, B4, B3, B2, B1, B0. There are four levels of transmit
priority. If TXP bits for a particular message buffer are
set to ‘11’, that buffer has the highest possible priority.
If TXP bits for a particular message buffer are ‘00’, that
buffer has the lowest possible priority.
TXB2
priority
TRANSMIT PRIORITY
is
 2004 Microchip Technology Inc.
a
TXB3-TXB8
prioritization
within
the