PIC18F6585-I/PT Microchip Technology Inc., PIC18F6585-I/PT Datasheet - Page 171

• Manufacturer Part Number: PIC18F6585-I/PT
• Description: 64 PIN, 48 KB FLASH, 3328 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6585-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 48K Bytes
• Ram Size: 3.3K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.1
Both CCP1 and CCP2 are comprised of two 8-bit
registers: CCPRxL (low byte) and CCPRxH (high byte),
1
operation of CCPx. All are readable and writable.
Table 15-1 shows the timer resources of the CCP
module modes.
TABLE 15-1:
15.2
In Capture mode, CCPRxH:CCPRxL captures the
16-bit value of the TMR1 or TMR3 register when an
event occurs on pin CCPn. An event is defined as:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
TABLE 15-2:
 2004 Microchip Technology Inc.
Capture
Capture
Compare
PWM
PWM
PWM
x
CCP1
Mode
2. The CCPxCON register controls the
CCP Mode
Compare
CCP Module
Capture Mode
Capture
PWM
Capture
Compare
Compare
PWM
Capture
Compare
CCP MODE – TIMER
RESOURCE
INTERACTION OF CCP MODULES
Mode
CCP2
TMR1 or TMR3 time base. Time base can be different for each CCP.
The compare could be configured for the special event trigger which clears either TMR1
or TMR3 depending upon which time base is used.
The compare(s) could be configured for the special event trigger which clears TMR1 or
TMR3 depending upon which time base is used.
The PWMs will have the same frequency and update rate (TMR2 interrupt).
None.
None.
Timer Resource
Timer1 or Timer3
Timer1 or Timer3
Timer2
PIC18F6585/8585/6680/8680
An event is selected by control bits CCPxM3:CCPxM0
(CCPxCON<3:0>). When a capture is made, the inter-
rupt request flag bit, CCPxIF (PIR registers), is set. It
must be cleared in software. If another capture occurs
before the value in register CCPRx is read, the old
captured value will be lost.
15.2.1
In Capture mode, the CCPx pin should be configured
as an input by setting the appropriate TRIS bit.
15.2.2
The timer used with each CCP module is selected in
the T3CCP2:T3CCP1 bits of the T3CON register. The
timers used with the capture feature (either Timer1 or
Timer3) must be running in Timer mode or Synchro-
nized Counter mode. In Asynchronous Counter mode,
the capture operation may not work.
Note:
Interaction
CCP PIN CONFIGURATION
If the CCPx is configured as an output, a
write to the port can cause a capture
condition.
TIMER1/TIMER3 MODE SELECTION
DS30491C-page 169