P89LPC936FDH-T NXP Semiconductors, P89LPC936FDH-T Datasheet - Page 48

• Manufacturer Part Number: P89LPC936FDH-T
• Description: MCU 8-Bit 89LP 80C51 CISC 16KB Flash 2.5V/3.3V 28-Pin TSSOP T/R
• Manufacturer: NXP Semiconductors

Specifications of P89LPC936FDH-T

• Package: 28TSSOP
• Device Core: 80C51
• Family Name: 89LP
• Maximum Speed: 18 MHz
• Ram Size: 768 Byte
• Program Memory Size: 16 KB
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 26
• Interface Type: I2C/SPI/UART
• On-chip Adc: 8-chx8-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 2

NXP Semiconductors
P89LPC933_934_935_936
Product data sheet
Fig 22. Watchdog timer in Watchdog mode (WDTE = 1)
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed
sequence.
watchdog
oscillator
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
PCLK
8.26.1 Software reset
8.26.2 Dual data pointers
8.25 Watchdog timer
8.26 Additional features
The watchdog timer causes a system reset when it underflows as a result of a failure to
feed the timer prior to the timer reaching its terminal count. It consists of a programmable
12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap
taken from the prescaler. The clock source for the prescaler is either the PCLK or the
nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a
power-on reset. When the watchdog feature is disabled, it can be used as an interval
timer and may generate an interrupt.
mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the
watchdog clock and the CPU is powered-down, the watchdog is disabled. The watchdog
timer has a time-out period that ranges from a few μs to a few seconds. Please refer to the
P89LPC933/934/935/936 User manual for more details.
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,
as if an external reset or watchdog reset had occurred. Care should be taken when writing
to AUXR1 to avoid accidental software resets.
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the
address used with certain instructions. The DPS bit in the AUXR1 register selects one of
the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS
bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1
register, without the possibility of inadvertently altering other bits in the register.
WDCON (A7H)
÷32
PRE2
All information provided in this document is subject to legal disclaimers.
PRESCALER
PRE1
Rev. 8 — 12 January 2011
8-bit microcontroller with accelerated two-clock 80C51 core
PRE0
SHADOW REGISTER
Figure 22
P89LPC933/934/935/936
-
-
8-BIT DOWN
shows the watchdog timer in Watchdog
WDL (C1H)
COUNTER
WDRUN
WDTOF
WDCLK
© NXP B.V. 2011. All rights reserved.
002aaa905
reset
(1)
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