P89LPC936FDH-T NXP Semiconductors, P89LPC936FDH-T Datasheet - Page 66
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P89LPC936FDH-T
Manufacturer Part Number
P89LPC936FDH-T
Description
MCU 8-Bit 89LP 80C51 CISC 16KB Flash 2.5V/3.3V 28-Pin TSSOP T/R
Manufacturer
NXP Semiconductors
Datasheet
1.P89LPC936FDH518.pdf
(77 pages)
Specifications of P89LPC936FDH-T
Package
28TSSOP
Device Core
80C51
Family Name
89LP
Maximum Speed
18 MHz
Ram Size
768 Byte
Program Memory Size
16 KB
Operating Supply Voltage
2.5|3.3 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
26
Interface Type
I2C/SPI/UART
On-chip Adc
8-chx8-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
2
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Table 14.
V
T
P89LPC933_934_935_936
Product data sheet
Symbol
t
t
t
VR
RH
RL
amb
Fig 30. SPI slave timing (CPHA = 1)
DD
= 2.4 V to 3.6 V, unless otherwise specified.
= −40 °C to +85 °C for industrial, −40 °C to +125 °C for extended, unless otherwise specified.
Dynamic characteristics, ISP entry mode
Parameter
RST delay from V
RST HIGH time
RST LOW time
(CPOL = 0)
(CPOL = 1)
12.2 ISP entry mode
SPICLK
SPICLK
(output)
(input)
(input)
(input)
MISO
MOSI
t
SPIA
SS
Fig 31. ISP entry timing
t
SPILEAD
t
t
DD
SPIOH
SPIF
t
not defined
t
SPIF
SPIDV
active time
V
t
t
RST
SPICLKH
SPICLKL
All information provided in this document is subject to legal disclaimers.
t
DD
SPIF
t
SPIDSU
slave MSB/LSB out
MSB/LSB in
T
SPICYC
Rev. 8 — 12 January 2011
Conditions
t
SPIOH
t
t
t
SPICLKH
t
SPICLKL
SPIDV
SPIDH
8-bit microcontroller with accelerated two-clock 80C51 core
t
SPIR
t
VR
t
RL
t
SPIR
t
RH
P89LPC933/934/935/936
t
SPIOH
t
SPIDV
Min
50
1
1
t
SPIDSU
slave LSB/MSB out
LSB/MSB in
Typ
-
-
-
t
t
SPIDH
SPILAG
002aaa911
002aaa912
t
SPIR
Max
-
32
-
© NXP B.V. 2011. All rights reserved.
t
SPIDIS
Unit
μs
μs
μs
66 of 77
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