DS26519GN+ Maxim Integrated Products, DS26519GN+ Datasheet
DS26519GN+
Specifications of DS26519GN+
Related parts for DS26519GN+
DS26519GN+ Summary of contents
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... DS26519G+ 0°C to +70°C DS26519GN -40°C to +85°C DS26519GN+ -40°C to +85°C + Denotes a lead-free/RoHS compliant device. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. ...
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DETAILED DESCRIPTION.................................................................................................9 2. FEATURE HIGHLIGHTS ..................................................................................................10 2.1 G ......................................................................................................................................10 ENERAL 2 ............................................................................................................................10 INE NTERFACE 2 LOCK YNTHESIZERS 2 .....................................................................................................................10 ITTER TTENUATOR 2 ....................................................................................................................11 RAMER ORMATTER 2 ......................................................................................................................11 YSTEM NTERFACE ...
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Maintenance and Alarms ..................................................................................................................... 72 9.9.8 Alarms .................................................................................................................................................. 75 9.9.9 Error Count Registers .......................................................................................................................... 77 9.9.10 DS0 Monitoring Function...................................................................................................................... 79 9.9.11 Transmit Per-Channel Idle Code Generation ...................................................................................... 80 9.9.12 Receive Per-Channel Idle Code Insertion............................................................................................ 80 9.9.13 Per-Channel Loopback ........................................................................................................................ ...
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AC TIMING CHARACTERISTICS ..................................................................................289 13 ICROPROCESSOR 13.1.1 SPI Bus Mode .................................................................................................................................... 289 13.2 JTAG I T NTERFACE IMING 13 YSTEM LOCK 14. JTAG BOUNDARY SCAN AND TEST ACCESS PORT ................................................302 14.1 TAP C ...
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Figure 7-1. Block Diagram ......................................................................................................................................... 18 Figure 7-2. Detailed Block Diagram........................................................................................................................... 19 Figure 9-1. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 0 ............................................... 34 Figure 9-2. SPI Serial Port Access for Read Mode, SPI_CPOL = ...
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Figure 11-17. E1 Receive-Side Timing.................................................................................................................... 278 Figure 11-18. E1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................ 278 Figure 11-19. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)............................................ 279 Figure 11-20. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)............................................ 279 Figure ...
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Table 4-1. T1-Related Telecommunications Specifications ...................................................................................... 14 Table 4-2. E1-Related Telecommunications Specifications ...................................................................................... 15 Table 5-1. Time Slot Numbering Schemes................................................................................................................ 16 Table 8-1. Detailed Pin Descriptions ......................................................................................................................... 20 Table 9-1. CLKO Frequency Selection ...................................................................................................................... 37 Table 9-2. Reset Functions........................................................................................................................................ 38 ...
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Table 10-2. Global Register Mapping ...................................................................................................................... 109 Table 10-3. Global Register List .............................................................................................................................. 109 Table 10-4. Framer Register List ............................................................................................................................. 110 Table 10-5. LIU Register List ................................................................................................................................... 117 Table 10-6. BERT Register List ............................................................................................................................... 117 Table 10-7. Global Register Bit ...
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DETAILED DESCRIPTION The DS26519 is an 16-port monolithic device featuring independent transceivers that can be software configured for T1, E1 operation. Each transceiver is composed of a line interface unit, framer, HDLC controller, elastic store, and a ...
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FEATURE HIGHLIGHTS 2.1 General 23mm x 23mm, 484-pin HSBGA (1.00mm pitch) 3.3V and 1.8V supply with 5V tolerant inputs and outputs IEEE 1149.1 JTAG boundary scan Development support includes evaluation kit, driver source code, and reference designs 2.2 Line ...
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Framer/Formatter Fully independent transmit and receive functionality Full receive and transmit path transparency T1 framing formats D4 and ESF per T1.403 and expanded SLC-96 support (TR-TSY-008) E1 FAS framing and CRC-4 multiframe per G.704/G.706, and G.732 CAS multiframe Transmit-side ...
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Signaling freezing Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode User-selectable synthesized clock output 2.7 HDLC Controllers One HDLC controller engine for each T1/E1 port Independent 64-byte Rx and Tx buffers with ...
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APPLICATIONS The DS26519 is useful in applications such as: Routers Channel Service Units (CSUs) Data Service Units (DSUs) Muxes Switches Channel Banks T1/E1 Test Equipment DS26519 16-Port T1/E1/J1 Transceiver 13 of 310 ...
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SPECIFICATIONS COMPLIANCE The DS26519 meets all the latest relevant telecommunications specifications. specifications and Table 4-2 provides the E1 specifications and relevant sections that are applicable to the DS26519. Table 4-1. T1-Related Telecommunications Specifications ANSI T1.102: Digital Hierarchy Electrical Interface ...
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Table 4-2. E1-Related Telecommunications Specifications ITU-T G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces Defines the 2048kbps bit rate—2048 ±50ppm; the transmission media are 75Ω coax or 120Ω twisted pair; peak-to- peak space voltage is ±0.237V; nominal pulse width is ...
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ACRONYMS AND GLOSSARY This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In each 125μs T1 frame, there are 24 8-bit channels plus a framing bit assumed that the framing bit is ...
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MAJOR OPERATING MODES The DS26519 has two major modes of operation: T1 mode and E1 mode. The mode of operation for each LIU is configured in the LTRCR register. The mode of operation for each framer is configured in ...
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BLOCK DIAGRAMS Figure 7-1. Block Diagram DS26519 LIU #4 LIU #3 LIU #2 RTIP RTIPE LINE RRING INTERFACE TTIP UNIT TRING x16 MICRO PROCESSOR INTERFACE CONTROLLER PORT LIU #16 FRAMER #16 LIU #15 FRAMER #15 LIU #14 FRAMER #14 ...
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Figure 7-2. Detailed Block Diagram TRANSCEIVER TRANSMIT TTIPn LIU Waveform Shaper/Line TRINGn Driver RECEIVE RTIPn RTIPEn LIU Clock/Data RRINGn Recovery MICROPROCESSOR INTERFACE Serial Interface Mode: (SCLK, CPOL, CPHA, SPI SWAP, MOSI, and MISO) DS26519 Tx BERT HDLC ...
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PIN DESCRIPTIONS 8.1 Pin Functional Description Table 8-1. Detailed Pin Descriptions NAME PIN TTIP1 C5, D5 TTIP2 N4, N5 TTIP3 T4, T5 TTIP4 V3, V4 TTIP5 W18, Y18 TTIP6 K18, K19 TTIP7 G18, G19 TTIP8 F18, F19 TTIP9 V12, ...
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NAME PIN TYPE RTIP1 B4 RTIP2 T2 RTIP3 U1 RTIP4 Y2 RTIP5 AA20 RTIP6 J21 RTIP7 G21 Analog RTIP8 C21 Input RTIP9 AB13 RTIP10 AB15 RTIP11 AB17 RTIP12 M22 RTIP13 A11 RTIP14 A9 RTIP15 B6 RTIP16 N1 RRING1 A4 RRING2 ...
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NAME PIN TYPE TSER1 B15 TSER2 D14 TSER3 T8 TSER4 R12 TSER5 T10 TSER6 U11 TSER7 C17 TSER8 E17 Input TSER9 U21 TSER10 R20 TSER11 W6 TSER12 C1 TSER13 E1 TSER14 H1 TSER15 H15 TSER16 F17 TCLK1 F7 TCLK2 G10 ...
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NAME PIN TYPE TSYNC1/ F8 TSSYNCIO1 TSYNC2/ D13 TSSYNCIO2 TSYNC3/ R9 TSSYNCIO3 TSYNC4/ AB3 TSSYNCIO4 TSYNC5/ AA7 TSSYNCIO5 TSYNC6/ AA9 TSSYNCIO6 TSYNC7/ D20 TSSYNCIO7 TSYNC8/ H16 TSSYNCIO8 Input/ Output TSYNC9/ K15 TSSYNCIO9 TSYNC10/ N16 TSSYNCIO10 TSYNC11/ Y6 TSSYNCIO11 TSYNC12/ M8 ...
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NAME PIN TYPE TCHBLK1/ A15 TCHCLK1 TCHBLK2/ A17 TCHCLK2 TCHBLK3/ N9 TCHCLK3 TCHBLK4/ V8 TCHCLK4 TCHBLK5/ V9 TCHCLK5 TCHBLK6/ W10 TCHCLK6 TCHBLK7/ E14 TCHCLK7 TCHBLK8/ H12 TCHCLK8 Output TCHBLK9/ N20 TCHCLK9 TCHBLK10/ W22 TCHCLK10 TCHBLK11/ Y5 TCHCLK11 TCHBLK12/ K6 TCHCLK12 ...
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NAME PIN TYPE RSER1 D12 RSER2 E12 RSER3 J5 RSER4 AA4 RSER5 Y10 RSER6 AA10 RSER7 B18 RSER8 T20 Output RSER9 L17 RSER10 L16 RSER11 B1 RSER12 K7 RSER13 J4 RSER14 P7 RSER15 H13 RSER16 M16 RCLK1 J9 RCLK2 H7 ...
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NAME PIN TYPE RSYNC1 F9 RSYNC2 E13 RSYNC2 T7 RSYNC2 W3 RSYNC5 W9 RSYNC6 AB9 RSYNC7 A19 RSYNC8 Y19 Input/ Output RSYNC9 N19 RSYNC10 P17 RSYNC11 V5 RSYNC12 L7 RSYNC13 L6 RSYNC14 L5 RSYNC15 E15 RSYNC16 R18 RMSYNC1/ C13 RFSYNC1 ...
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NAME PIN TYPE RSIG1 D4 RSIG2 B16 RSIG3 J7 RSIG4 R10 RSIG5 U10 RSIG6 V11 RSIG7 H17 RSIG8 V19 Ouptut RSIG9 F6 RSIG10 P20 RSIG11 D2 RSIG12 Y4 RSIG13 J3 RSIG14 K3 RSIG15 J14 RSIG16 P15 GPIO1 P22 GPIO2 J17 ...
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NAME PIN TYPE RCHBLK1/ F3 RCHCLK1 RCHBLK2/ G8 RCHCLK2 RCHBLK3/ H5 RCHCLK3 RCHBLK4/ Y7 RCHCLK4 RCHBLK5/ AA8 RCHCLK5 RCHBLK6/ AA11 RCHCLK6 RCHBLK7/ E18 RCHCLK7 RCHBLK8/ U20 RCHCLK8 Output RCHBLK9/ G7 RCHCLK9 RCHBLK10/ L15 RCHCLK10 RCHBLK11/ B2 RCHCLK11 RCHBLK12/ W4 RCHCLK12 ...
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NAME PIN TYPE A13 C16 A12 F12 A11 A20 A10 G11 A21 A7 F13 Input A6 A22 A5 H10 A4 B19 A3 H11 A2 D15 A1 G13 A0 B20 D[7]/ Y9 Input SPI_CPOL D[6]/ U8 Input SPI_CPHA ...
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NAME PIN TYPE WRB / R13 Input RWB Output/ INTB U9 Tri- Stateable SPI_SEL F5 Input BTS U15 Input MCLK F11 Input RESETB T16 Input Input/ REFCLKIO A18 Output Input, DIGIOEN A14 Pullup Input, JTRST F4 Pullup Input, JTMS G4 ...
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NAME PIN TYPE ATVDD1 C4 ATVDD2 T1 ATVDD3 T3 ATVDD4 AA2 ATVDD5 AA21 ATVDD6 H21 ATVDD7 E21 ATVDD8 C20 — ATVDD9 AB11 ATVDD10 Y15 ATVDD11 AA19 ATVDD12 K21 ATVDD13 B11 ATVDD14 A8 ATVDD15 B7 ATVDD16 L1 ATVSS1 B3 ATVSS2 R3 ...
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NAME PIN TYPE ARVSS1 A2 ARVSS2 N3 ARVSS3 W2 ARVSS4 AB1 ARVSS5 AB22 ARVSS6 J20 ARVSS7 G20 ARVSS8 D21 — ARVSS9 AA14 ARVSS10 Y13 ARVSS11 AB19 ARVSS12 K20 ARVSS13 A10 ARVSS14 C10 ARVSS15 C7 ARVSS16 P2 ACVDD L14, M9 — ...
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FUNCTIONAL DESCRIPTION 9.1 Processor Interface Microprocessor control of the DS26519 is accomplished through the 28 hardware pins of the microprocessor port. The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the bus ...
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SPI_CPOL and SPI_CPHA pins to describe which type of clock that the master device is providing. Figure 9-1. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 0 SPI_SCLK CSB SPI_MOSI 1 A13 ...
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Figure 9-5. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 0 SPI_SCLK CSB 0 A13 A12 A11 A10 SPI_MOSI MSB SPI_MISO Figure 9-6. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 0 ...
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This register is also used to program REFCLKIO as an input or output. REFCLKIO can be an output sourcing MCLKT1 or MCLKE1 as shown in This backplane clock and frame pulse (TSSYNCIOn) can be used by the DS26519 and ...
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CLKO Output Clock Generation This clock output is derived from MCLK based upon the setting of the CLKOSEL[2:0] bits in the register.The reference for the PLL is not the input clock on MCLK, but the scaled version of MCLK ...
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Resets and Power-Down Modes A hardware reset is issued by forcing the RESETB pin to logic low. The RESETB input pin resets all framers, LIUs, and BERTs. Note that not all registers are cleared to 00h on a reset ...
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Initialization and Configuration 9.4.1 Example Device Initialization and Sequence STEP 1: Reset the device by pulling the RESETB pin low, applying power to the device using the software reset bits outlined in Section 9.2.2. Clear all reset ...
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Global Resources All 16 framers share a common microprocessor port and a common MCLK. There are two common software- configurable BPCLK outputs (BPCLK[2:1]. A set of global registers includes global resets, global interrupt status, interrupt masking, clock configuration, and ...
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Device Interrupts Figure 9-11 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the global ...
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Figure 9-11. Device Interrupt Information Flow Diagram Receive Remote Alarm Indication Clear Receive Alarm Condition Clear Receive Loss of Signal Clear Receive Loss of Frame Clear Receive Remote Alarm Indication Receive Alarm Condition Receive Loss of Signal Receive Loss of ...
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System Backplane Interface The DS26519 provides a versatile backplane interface that can be configured to: • Transmit and receive two-frame elastic stores • Mapping of T1 channels into a 2.048MHz backplane • IBO mode for multiple framers to share ...
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Elastic Stores Initialization There are two elastic store initializations that may be used to improve performance in certain applications: elastic store reset and elastic store align. Both of these involve the manipulation of the elastic store’s read and write ...
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Receiving Mapped T1 Channels from a 2.048MHz Backplane Setting the TSCLKM bit in TIOCR.4 enables the transmit elastic store to operate with a 2.048MHz backplane (32 time slots / frame). In this mode the user can choose which of ...
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Mapping E1 Channels onto a 1.544MHz Backplane The user can use the RSCLKM bit in RIOCR.4 to enable the receive elastic store to operate with a 1.544MHz backplane (24 channels / frame + F-bit). In this mode the user ...
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Figure 9-12. IBO Multiplexer Equivalent Circuit—4.096MHz Figure 9-12. IBO Multiplexer Equivalent Circuit—4.096MHz Port # 1 Port # 1 Backplane Backplane Interface Interface Port # 2 Port # 2 Backplane Backplane Interface Interface Port # 3 Port # 3 Backplane Backplane ...
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Figure 9-13. IBO Multiplexer Equivalent Circuit—8.192MHz Port # 1 Backplane Interface Port # 2 Backplane Interface Port # 3 Backplane Interface Port # 4 Backplane Interface Port # 5 Backplane Interface Port # 6 Backplane Interface Port # 7 Backplane ...
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Figure 9-14. IBO Multiplexer Equivalent Circuit—16.384MHz Port # 1 Backplane Interface Port # 2 Backplane Interface Port # 3 Backplane Interface Port # 4 Backplane Interface Port # 5 Backplane Interface Port # 6 Backplane Interface Port # 7 Backplane ...
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Table 9-6. RSERn Output Pin Definitions (GTCR1.GIBO = 0) PIN NORMAL USE Receive Serial Data RSER1 for Port 1 Receive Serial Data RSER2 for Port 2 Receive Serial Data RSER3 for Port 3 Receive Serial Data RSER4 for Port 4 ...
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Table 9-7. RSIGn Output Pin Definitions (GTCR1.GIBO = 0) PIN NORMAL USE Receive Signaling RSIG1 Data for Port 1 Receive Signaling RSIG2 Data for Port 2 Receive Signaling RSIG3 Data for Port 3 Receive Signaling RSIG4 Data for Port 4 ...
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Table 9-8. TSERn Input Pin Definitions (GTCR1.GIBO = 0) PIN NORMAL USE Transmit Serial Data TSER1 for Port 1 Transmit Serial Data TSER2 for Port 2 Transmit Serial Data TSER3 for Port 3 Transmit Serial Data TSER4 for Port 4 ...
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Table 9-9. TSIGn Input Pin Definitions (GTCR1.GIBO = 0) PIN NORMAL USE Transmit Signaling TSIG1 Data for Port 1 Transmit Signaling TSIG2 Data for Port 2 Transmit Signaling TSIG3 Data for Port 3 Transmit Signaling TSIG4 Data for Port 4 ...
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Table 9-10. RSYNCn Input Pin Definitions (GTCR1.GIBO = 0) PIN NORMAL USE Receive Frame Pulse RSYNC1 for Port 1 Receive Frame Pulse RSYNC2 for Port 2 Receive Frame Pulse RSYNC3 for Port 3 Receive Frame Pulse RSYNC4 for Port 4 ...
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H.100 (CT Bus) Compatibility The H.100 (or CT bus synchronous, bit-serial, TDM transport bus operating at 8.192MHz. The H.100 standard also allows compatibility modes to operate at 2.048MHz, 4.096MHz, or 8.192MHz. The control bit H100EN (RIOCR.5), when ...
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Figure 9-15. RSYNCn Input in H.100 (CT Bus) Mode 1 RSYNCn 2 RSYNCn RSYSCLKn BIT 8 RSERn NOTE 1: RSYNCn INPUT MODE IN NORMAL OPERATION. NOTE 2: RSYNCn INPUT MODE, H100EN = 1 AND RSYNCINV = 1. NOTE 3: t ...
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Transmit and Receive Channel Blocking Registers The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLKn and TCHBLKn pins, respectively. The RCHBLKn and TCHBLKn pins are user-programmable outputs that can be forced either ...
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Framers The DS26519 framer cores are software selectable for T1, J1, or E1. The receive framer locates the frame and multiframe boundaries and monitors the data stream for alarms also used for extracting and inserting signaling data, ...
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Table 9-12. ESF Framing Mode FRAME FRAMING NUMBER Table 9-13. SLC-96 ...
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FRAME NUMBER ...
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E1 Framing The E1 framing consists of FAS, NFAS detection as shown in Table 9-14. E1 FAS/NFAS Framing CRC-4 FRAME TYPE FAS C1 1 NFAS 0 2 FAS C2 3 NFAS 0 4 FAS C3 5 ...
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Table 9-15 shows the registers that are related to setting up the framing. Table 9-15. Registers Related to Setting Up the Framer REGISTER Transmit Master Mode Register (TMMR) Transmit Control Register 1 (TCR1) Transmit Control Register 2 (T1.TCR2) Transmit Control ...
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T1 Transmit Synchronizer The DS26519 transmitter can identify the D4 or ESF frame boundary, as well as the CRC multiframe boundaries within the incoming NRZ data stream at TSERn. The TFM (TCR3.2) control bit determines whether the transmit synchronizer ...
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Signaling The DS26519 supports both software and hardware-based signaling. Interrupts can be generated on changes of signaling data. The DS26519 is also equipped with receive-signaling freeze on loss of synchronization (OOF), carrier loss or change of frame alignment. The ...
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Transmit-Signaling Operation There are two methods to provide transmit-signaling data. These are processor based (i.e., software based) or hardware based. Processor-based refers to access through the transmit signaling registers, TS1–TS16, while hardware based refers to using the TSIGn pins. ...
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Receive-Signaling Operation There are two methods to access receive-signaling data and provide transmit-signaling data: processor based (i.e., software based) or hardware based. Processor-based refers to access through the transmit- and receive-signaling registers, RS1–RS16. Hardware based refers to the RSIGn ...
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Receive-Signaling Freeze The signaling data in the four multiframe signaling buffers will be frozen in a known good state upon either a loss of synchronization (OOF event), carrier loss, or change of frame alignment mode, this action ...
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Receive SLC-96 Operation (T1 Mode Only SLC-96-based transmission scheme, the standard Fs-bit pattern is robbed to make room for a set of message fields. The SLC-96 multiframe is made up of six D4 superframes, hence it is ...
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T1 Data Link 9.9.5.1 T1 Transmit Bit-Oriented Code (BOC) Transmit Controller The DS26519 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. Table ...
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Legacy T1 Transmit FDL It is recommended that the DS26519’s built-in BOC or HDLC controllers be used for most applications requiring access to the FDL. Table 9-21 shows the registers related to control of the transmit FDL. Table 9-21. ...
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E1 Data Link Table 9-23 shows the registers related to E1 data link. Table 9-23. Registers Related to E1 Data Link REGISTER E1 Receive Align Frame Register (E1RAF) E1 Receive Non-Align Frame Register Register (E1RNAF) E1 Received Si Bits ...
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Additional E1 Receive Sa- and Si-Bit Receive Operation (E1 Mode) The DS26519, when operated in the E1 mode, provides for access to both the Sa and the Si bits via two methods. The first involves using the internal an ...
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Table 9-24 shows some of the registers related to maintenance and alarms. Table 9-24. Registers Related to Maintenance and Alarms REGISTER Receive Real-Time Status Register 1 (RRTS1) Receive Interrupt Mask Register 1(RIM1) Receive Latched Status Register 2 (RLS2) Receive Real-Time ...
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Status and Information Bit Operation When a particular event has occurred (or is occurring), the appropriate bit in one of these registers will be set to a one. Status bits may operate in either a latched or real-time fashion. ...
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Alarms Table 9-25. T1 Alarm Criteria ALARM AIS (Blue Alarm) (See Note Bit 2 Mode (T1RCR2 12th F-Bit Mode (T1RCR2 (Note: This mode is also referred to as the RAI ...
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Receive RAI Table 9-27 shows the registers related to the receive RAI (Yellow Alarm). Table 9-27. Registers Related to Receive RAI (Yellow Alarm) REGISTER Receive Control Register 2 (T1RCR2.RRAIS) Receive Control Register 2 (T1RCR2.RAIIE) Note: The addresses shown above ...
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Error Count Registers The DS26519 contains four counters that are used to accumulate line coding errors, path errors, and synchronization errors. Counter update options include one second boundaries, 42ms (T1 mode only), 62.5ms (E1 mode only) or manually. See ...
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Path Code Violation Count Register (PCVCR operation, the Path Code Violation Count Register records either Ft, Fs, or CRC-6 errors. When the receive side of a framer is set to operate in the T1 ESF framing mode, ...
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DS0 Monitoring Function The DS26519 can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. Table 9-32 Table 9-32. Registers Related to DS0 Monitoring REGISTER Transmit DS0 ...
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Transmit Per-Channel Idle Code Generation Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. The Transmit Idle Code Definition Registers (TIDR1–32) are provided to set the 8-bit idle code ...
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T1 Programmable In-Band Loop Code Generator The DS26519 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. Table 9-33. Registers Related to ...
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T1 Programmable In-Band Loop Code Detection The DS26519 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. Table 9-34. Registers Related to ...
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Framer Payload Loopbacks The framer, payload, and remote loopbacks are controlled by RCR3. Table 9-35. Register Related to Framer Payload Loopbacks RECEIVE CONTROL FRAMER 1 REGISTER 3 (RCR3) ADDRESSES Framer Loopback Payload Loopback Remote Loopback Note: The addresses shown ...
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HDLC Controllers 9.10.1 Receive HDLC Controller This device has an enhanced HDLC controller that can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). The HDLC controller has 64-byte ...
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HDLC FIFO Control Control of the transmit and receive FIFOs is accomplished via the Receive HDLC FIFO Control (RHFC) and Transmit HDLC FIFO Control (THFC) registers. The FIFO control registers set the watermarks for the FIFO. When the receive ...
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Figure 9-18. HDLC Message Receive Example Start New Start New Message Buffer Message Buffer Configure Receive HDLC Controller (RHC, RHBSE, RHFC) Reset Receive HDLC Controller (RHC.6) Start New Start New Message Buffer Message Buffer Enable Interrupts RPE and RHWM NO ...
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Transmit HDLC Controller 9.10.2.1 FIFO Information The Transmit HDLC FIFO Buffer Available Register (TFBA) indicates the number of bytes that can be written into the transmit FIFO. The count from this register informs the host as to how many ...
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Figure 9-19. HDLC Message Transmit Example Loop Action Required Work Another Process Configure Transmit HDLC Controller (THC1,THC2,THBSE,THFC) Reset Transmit HDLC Controller (THC.5) Enable TLWM Interrupt and Verify TLWM Clear Read TFBA N = TFBA[6..0] Push Message Byte ...
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Power-Supply Decoupling Table 9-37. Recommended Supply Decoupling SUPPLY PINS DECOUPLING CAPACITANCE DVDD33/DVSS 0.01μF + 0.1μF + 1μF + 10μF DVDD18/DVSS 0.01μF + 0.1μF + 1μF + 10μF ATVDD/ATVSS 0.1μF (x16) + 1μF (x8) + 10μF (x4) ARVDD/ARVSS 0.1μF (x16) ...
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Line Interface Units (LIUs) The DS26519 has 16 identical LIU transmit and receive front-ends for each of the 16 framers. Each LIU contains three sections: the transmitter, which waveshapes and drives the network line; the receiver, which handles clock ...
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Figure 9-20. Network Connection—Longitudinal Protection F1 TX TIP S7 TX RING TIP S8 RX RING F4 NAME DESCRIPTION 1.25A Slow Blow Fuse 1.25A Slow Blow Fuse S1, S2 25V (max) Transient Suppressor S3, S4, ...
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LIU Operation The analog AMI/HDB3 waveforms off of the E1 lines or the AMI/B8ZS waveform off of the T1 lines are transformer coupled into the RTIPn and RRINGn pins of the DS26519. The user has the option to use ...
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Transmitter NRZ data arrives from the framer transmitter; the data is encoded with HDB3 or B8ZS or AMI. The encoded data passes through a jitter attenuator enabled for the transmit path. A digital sequencer and DAC ...
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Transmit-Line Pulse Shapes The DS26519 transmitters can be selected individually to meet the pulse templates for E1 and T1/J1 modes. The T1/J1 pulse template is shown in shape can be configured for each LIU on an individual basis. The ...
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Figure 9-22. E1 Transmit Pulse Templates 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 194ns 219ns -200 -150 -100 - TIME (ns 310 DS26519 16-Port T1/E1/J1 Transceiver 269ns ...
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Transmit G.703 Section 10 Synchronization Signal The DS26519 can transmit a 2.048MHz square-wave synchronization clock as specified in Section 10 of ITU-T G.703. To use this mode, set the transmit G.703 synchronization clock bit (TG703) found in the LIU ...
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Receiver 9.12.3.1 Receive Internal Termination The DS26519 contains 16 receivers. The termination circuit provides an analog switch that powers up in the open setting, providing high impedance to the receive line side. This is useful for redundancy applications and ...
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The DS26519 uses a digital clock recovery system. The resultant E1 clock derived from MCLK is multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock recovery system uses the clock ...
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For short-haul mode, the loss-detection thresholds are based on cable loss of 12dB to 18dB for both T1/J1 and E1 modes. The loss thresholds are selectable based on is based on cable loss of 30dB to 38dB for T1/J1 and ...
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Table 9-42. T1.231, G.775, and ETS 300 233 Loss Criteria Specifications CRITERIA T1.231 No pulses are detected for 175 Loss ±75 bits. Detection Loss is terminated if a duration of 12.5% ones are detected over duration of 175 ±75 bits. ...
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Hitless Protection Switching (HPS) Many current redundancy protection implementations use mechanical relays to switch between primary and backup boards. The switching time in relays is typically in the milliseconds, making T1/E1 HPS impossible. The switching event will likely cause ...
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Jitter Attenuator The DS26519 contains a jitter attenuator that can be set to a depth 128 bits via the JADS bits in LIU Transmit and Receive Control Register (LTRCR). The 128-bit mode is used in applications ...
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LIU Loopbacks The DS26519 provides four LIU loopbacks for diagnostic purposes: Analog Loopback, Local Loopback, Remote Loopback 1, and Remote Loopback 2. Dual Loopback is a combination of Local Loopback and Remote Loopback 1. In the loopback diagrams that ...
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Local Loopback The transmit system data is looped back to the receive framer. This data is also encoded and output on TTIPn and TRINGn. Signals at RTIPn and RRINGn are ignored. This loopback is conceptually shown in Figure 9-29. ...
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Dual Loopback The inputs decoded from the receive LIU are looped back to the transmit LIU. The inputs from the transmit framer are looped back to the receiver with the optional jitter attenuator. Dual Loopback is a combination of ...
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Bit Error-Rate Test Function (BERT) The BERT (Bit Error Rate Tester) block can generate and detect both pseudorandom and repeating bit patterns used to test and stress data-communication links. BERT functionality is dedicated for each of the ...
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The BERT block can generate and detect the following patterns: • The pseudorandom patterns 2E7-1, 2E9-1, 2E11-1, 2E15-1, and QRSS. • A repetitive pattern from bits in length. • Alternating (16-bit) words that flip every 1 to ...
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DEVICE REGISTERS Fourteen address bits are used to control the settings of the registers. The registers control functions of the framers, LIUs, and BERTs within the DS26519. The map is divided into 16 framers, followed by 16 LIUs and ...
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Global Register List Table 10-2. Global Register Mapping REGISTER ADDRESS CHANNEL 1–8 00F0–00FF 9–16 20F0–20FF Table 10-3. Global Register List ADDRESS NAME FRAMER 1 00F0h GTCR1 00F1h GFCR1 00F2h GTCR3 00F3h GTCCR1 00F4h GTCCR3 00F5h — 00F6h GSRR1 00F7h ...
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Framer Register List Table 10-4. Framer Register List Note that only Framer 1 address is presented here. The same set of registers definitions applies for transceivers accordance with the DS26519 map offsets. Transceiver offset is ...
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ADDRESS NAME RIDR30 T1RDMWE3 03Eh RIDR31 03Fh RIDR32 040h RS1 041h RS2 042h RS3 043h RS4 044h RS5 045h RS6 046h RS7 047h RS8 048h RS9 049h RS10 04Ah RS11 04Bh RS12 04Ch RS13 04Dh RS14 04Eh RS15 04Fh RS16 ...
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ADDRESS NAME 080h RMMR RCR1 081h RCR1 T1RIBCC 082h E1RCR2 083h RCR3 084h RIOCR 085h RESCR 086h ERCNT 087h RHFC 088h RIBOC 089h T1RSCC 08Ah RXPC 08Bh RBPBS 08Ch–08Fh — 090h RLS1 RLS2 091h RLS2 RLS3 092h RLS3 093h RLS4 ...
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ADDRESS NAME 0B1h — RRTS3 0B2h RRTS3 0B3h — 0B4h RRTS5 0B5h RHPBA 0B6h RHF 0B7h–0BFh — 0C0h RBCS1 0C1h RBCS2 0C2h RBCS3 0C3h RBCS4 0C4h RCBR1 0C5h RCBR2 0C6h RCBR3 0C7h RCBR4 0C8h RSI1 0C9h RSI2 0CAh RSI3 0CBh ...
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ADDRESS NAME 118h SSIE1 119h SSIE2 11Ah SSIE3 11Bh SSIE4 11Ch–11Fh — 120h TIDR1 121h TIDR2 122h TIDR3 123h TIDR4 124h TIDR5 125h TIDR6 126h TIDR7 127h TIDR8 128h TIDR9 129h TIDR10 12Ah TIDR11 12Bh TIDR12 12Ch TIDR13 12Dh TIDR14 ...
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ADDRESS NAME 150h TCICE1 151h TCICE2 152h TCICE3 153h TCICE4 154h–161h — 162h T1TFDL 163h T1TBOC T1TSLC1 164h E1TAF T1TSLC2 165h E1TNAF T1TSLC3 166h E1TSiAF 167h E1TSiNAF 168h E1TRA 169h E1TSa4 16Ah E1TSa5 16Bh E1TSa6 16Ch E1TSa7 16Dh E1TSa8 16Eh–17Fh ...
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ADDRESS NAME 1B4h THF 1B5h–1BAh — 1BBh TDS0M 1BCh–1BFh — 1C0h TBCS1 1C1h TBCS2 1C2h TBCS3 1C3h TBCS4 1C4h TCBR1 1C5h TCBR2 1C6h TCBR3 1C7h TCBR4 1C8h THSCS1 1C9h THSCS2 1CAh THSCS3 1CBh THSCS4 1CCh TGCCS1 1CDh TGCCS2 1CEh TGCCS3 ...
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LIU and BERT Register List Table 10-5. LIU Register List Note that only the LIU 1 address is presented here. The same set of registers definitions applies for LIUs accordance with the DS26519 map offsets. ...
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Register Bit Maps 10.2.1 Global Register Bit Map Table 10-7. Global Register Bit Map ADDR NAME BIT 7 (1–8) 00F0h GTCR1 GPSEL3 00F1h GFCR1 IBOMS1 00F2h GTCR3 — 00F3h GTCCR1 BPREFSEL3 BPREFSEL2 BPREFSEL1 BPREFSEL0 BFREQSEL FREQSEL — RSYSCLKSEL TSYSCLKSEL ...
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Framer Register Bit Map Table 10-8 contains the framer registers of the DS26519. Some registers have dual functionality based on the selection of T1/ operating mode in the shown below using two lines of text. The first ...
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ADDR NAME BIT 7 T1RSAOI3 CH24 03Ah RIDR27 C7 — 03Bh RIDR28 C7 T1RDMWE1 CH8 03Ch RIDR29 C7 T1RDMWE2 CH16 03Dh RIDR30 C7 T1RDMWE3 CH24 03Eh RIDR31 C7 — 03Fh RIDR32 C7 CH1-A 040h RS1 0 CH2-A 041h RS2 CH1-A ...
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ADDR NAME BIT 7 054h FOSCR1 FOS15 055h FOSCR2 FOS7 056h E1EBCR1 EB15 057h E1EBCR2 EB7 058h FEACR1 FEACR15 059h FEACR2 FEACR7 05Ah FEBCR1 FEBCR15 05Bh FEBCR2 FEBCR7 060h RDS0M B1 T1RFDL RFDL7 062h E1RRTS7 CSC5 063h T1RBOC — T1RSLC1 ...
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ADDR NAME BIT 7 093h RLS4 RESF 094h RLS5 — RLS7 (T1) — 096h RLS7 (E1) — 098h RSS1 CH8 099h RSS2 CH16 09Ah RSS3 CH24 — 09Bh RSS4 CH32 C7 09Ch T1RSCD1 — C7 09Dh T1RSCD2 — 09Fh RIIR ...
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ADDR NAME BIT 7 — 0C7h RCBR4 CH32 0C8h RSI1 CH8 0C9h RSI2 CH16 0CAh RSI3 CH24 — 0CBh RSI4 CH32 0CCh RGCCS1 CH8 0CDh RGCCS2 CH16 0CEh RGCCS3 CH24 — 0CFh RGCCS4 CH32 0D0h RCICE1 CH8 0D1h RCICE2 CH16 ...
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ADDR NAME BIT 7 128h TIDR9 C7 129h TIDR10 C7 12Ah TIDR11 C7 12Bh TIDR12 C7 12Ch TIDR13 C7 12Dh TIDR14 C7 12Eh TIDR15 C7 12Fh TIDR16 C7 130h TIDR17 C7 131h TIDR18 C7 132h TIDR19 C7 133h TIDR20 C7 ...
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ADDR NAME BIT 7 CH8-A CH10-A 149h TS10 CH9-A CH11-A 14Ah TS11 CH10-A CH12-A 14Bh TS12 CH11-A — 14Ch TS13 CH12-A — 14Dh TS14 CH13-A — 14Eh TS15 CH14-A — 14Fh TS16 CH15-A 150h TCICE1 CH8 151h TCICE2 CH16 152h ...
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ADDR NAME BIT 7 E1.TCR2 AEBE (E1) — 183h TCR3 — TCLKINV 184h TIOCR TCLKINV 185h TESCR TDATFMT uALAW 186h TCR4 uALAW 187h THFC — 188h TIBOC — 189h TDS0SEL — 18Ah TXPC — 18Bh TBPBS BPBSE8 — 18Eh TSYNCC ...
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ADDR NAME BIT 7 CH32 1CCh TGCCS1 CH8 1CDh TGCCS2 CH16 1CEh TGCCS3 CH24 — 1CFh TGCCS4 CH32 1D0h PCL1 CH8 1D1h PCL2 CH16 1D2h PCL3 CH24 — 1D3h PCL4 CH32 1D4h TBPCS1 CH8 1D5h TBPCS2 CH16 1D6h TBPCS3 CH24 ...
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LIU Register Bit Map Table 10-9. LIU Register Bit Map ADDR NAME BIT 7 1000h LTRCR — 1001h LTIPSR TG703 TIMPTON 1002h LMCR TAIS 1003h LRSR — 1004h LSIMR JALTCIM 1005h LLSR JALTC 1006h LRSL RSL3 1007h LRISMR REXTON ...
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BERT Register Bit Map Table 10-10. BERT Register Bit Map ADDR NAME BIT 7 1100h BAWC ACNT7 1101h BRP1 RPAT7 1102h BRP2 RPAT15 1103h BRP3 RPAT23 1104h BRP4 RPAT31 1105h BC1 TC 1106h BC2 EIB2 1107h BBC1 BBC7 1108h ...
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Global Register Definitions Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status, framer interrupt status, IBO configuration, MCLK configuration, and BPCLKn configuration. The global registers bit descriptions are presented below. Note: Each ...
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Register Name GTCR1 Register Description: Global Transceiver Control Register 1 Register Address: 00F0h Channels Bit # 7 6 Name GPSEL3 GPSEL2 Default 0 0 Bits General-Purpose I/O Pins Select (GPSEL[3:1]). GPSEL0 must be set ...
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Register Name GTCR2 Register Description: Global Transceiver Control Register 2 Register Address: 20F0h Channels Bit # 7 6 Name GPSEL3 GPSEL2 Default 0 0 Bits General-Purpose I/O Pins Select (GPSEL[3:1]). GPSEL0 must be set ...
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Register Name: GFCR1 Description: Global Framer Control Register 1 Register Address: 00F1h Channels Bit # 7 6 Name IBOMS1 IBOMS0 Default 0 0 Bits 7 and 6: Interleave Bus Operation Mode Select 1 and 0 (IBOMS[1:0]). These ...
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Register Name: GFCR2 Description: Global Framer Control Register 2 Register Address: 20F1h Channels Bit # 7 6 Name IBOMS1 IBOMS0 Default 0 0 Bits 7 and 6: Interleave Bus Operation Mode Select 1 and 0 (IBOMS[1:0]). These ...
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Register Name: GTCR3 Register Description: Global Transceiver Control Register 3 Register Address: 00F2h Channels Bit # 7 6 Name — — Default 0 0 Bit 1: Transmit System Synchronization I/O Select (TSSYNCIOSEL TSSYNCIO[8:1] are inputs ...
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Register Name: GTCCR1 Register Description: Global Transceiver Clock Control Register 1 Register Address: 00F3h Channels Bit # 7 6 Name BPREFSEL3 BPREFSEL2 Default 0 0 Bits Backplane Clock Reference Selects (BPREFSEL[3:0]). These bits select ...
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Table 10-15. Backplane Reference Clock Select ( BPREFSEL3 BPREFSEL2 ...
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Register Name: GTCCR2 Register Description: Global Transceiver Clock Control Register 2 Register Address: 20F3h Channels Bit # 7 6 Name BPREFSEL3 BPREFSEL2 Default 0 0 Bits Backplane Clock Reference Selects (BPREFSEL[3:0]). These bits select ...
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Register Name: GTCCR3 Register Description: Global Transceiver Clock Control Register 3 Register Address: 00F4h Channels Bit # 7 6 Name — RSYSCLKSEL Default 0 0 Bit 6: RSYSCLKn Select (RSYSCLKSEL Use RSYSCLKn pins for each ...
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Register Name: GTCCR4 Register Description: Global Transceiver Clock Control Register 4 Register Address: 20F4h Channels Bit # 7 6 Name — RSYSCLKSEL Default 0 0 Bit 6: RSYSCLKn Select (RSYSCLKSEL Use RSYSCLKn pins for each ...
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Register Name: GSRR1 Register Description: Global LIU Software Reset Register 1 Register Address: 00F6h Channels Bit # 7 6 Name — — Default 0 0 Bit 2: LIU Software Reset (LRST). LIU Channels 1–8 logic and registers ...
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Register Name: IDR Register Description: Device Identification Register Register Address: 00F8h Bit # 7 6 Name ID7 ID6 Default 1 1 Bits Device ID (ID[7:3]). The upper five bits of the IDR are used to display the ...
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Register Name: GFISR1 Register Description: Global Framer Interrupt Status Register 1 Register Address: 00F9h Channels Bit # 7 6 Name FIS8 FIS7 Default 0 0 The GFISR1 register reports the framer interrupt status for the T1/E1 framers ...
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Register Name: GFISR2 Register Description: Global Framer Interrupt Status Register 2 Register Address: 20F9h Channels Bit # 7 6 Name FIS16 FIS15 Default 0 0 The GFISR2 register reports the framer interrupt status for the T1/E1 framers ...
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Register Name: GBISR1 Register Description: Global BERT Interrupt Status Register 1 Register Address: 00FAh Channels Bit # 7 6 Name BIS8 BIS7 Default 0 0 The GBISR1 register reports the interrupt status for the T1/E1 bit error ...
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Register Name: GBISR2 Register Description: Global BERT Interrupt Status Register 2 Register Address: 20FAh Channels Bit # 7 6 Name BIS16 BIS15 Default 0 0 The GBISR2 register reports the interrupt status for the T1/E1 bit error ...
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Register Name: GLISR1 Register Description: Global LIU Interrupt Status Register 1 Register Address: 00FBh Channels Bit # 7 6 Name LIS8 LIS7 Default 0 0 The GLISR1 register reports the LIU interrupt status for the T1/E1 LIUs ...
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Register Name: GLISR2 Register Description: Global LIU Interrupt Status Register 2 Register Address: 20FBh Channels Bit # 7 6 Name LIS16 LIS15 Default 0 0 The GLISR2 register reports the LIU interrupt status for the T1/E1 LIUs ...
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Register Name: GFIMR1 Register Description: Global Framer Interrupt Mask Register 1 Register Address: 00FCh Channels Bit # 7 6 Name FIM8 FIM7 Default 0 0 Bit 7: Framer 8 Interrupt Mask (FIM8 Interrupt masked. 1 ...
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Register Name: GFIMR2 Register Description: Global Framer Interrupt Mask Register 2 Register Address: 20FCh Channels Bit # 7 6 Name FIM16 FIM15 Default 0 0 Bit 7: Framer 16 Interrupt Mask (FIM16 Interrupt masked. 1 ...
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Register Name: GBIMR1 Register Description: Global BERT Interrupt Mask Register 1 Register Address: 00FDh Channels Bit # 7 6 Name BIM8 BIM7 Default 0 0 Bit 7: BERT Interrupt Mask 8 (BIM8 Interrupt masked. 1 ...
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Register Name: GBIMR2 Register Description: Global BERT Interrupt Mask Register 2 Register Address: 20FDh Channels Bit # 7 6 Name BIM16 BIM15 Default 0 0 Bit 7: BERT Interrupt Mask 16 (BIM16 Interrupt masked. 1 ...
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Register Name: GLIMR1 Register Description: Global LIU Interrupt Mask Register 1 Register Address: 00FEh Channels Bit # 7 6 Name LIM8 LIM7 Default 0 0 Bit 7: LIU Interrupt Mask 8 (LIM8 Interrupt masked. 1 ...
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Register Name: GLIMR2 Register Description: Global LIU Interrupt Mask Register 2 Register Address: 20FEh Channels Bit # 7 6 Name LIM16 LIM15 Default 0 0 Bit 7: LIU Interrupt Mask 16 (LIM16 Interrupt masked. 1 ...
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Register Name: GPIORR1 Register Description: General-Purpose I/O Read Register 1 Register Address: 00FFh Channels Bit # 7 6 Name GPIO8 GPIO7 Default 0 0 Bits General-Purpose I/O Status [8:1] (GPIO[8:1]). These bits reflect the ...
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Framer Register Descriptions 10.4.1 Receive Register Descriptions See Table 10-4 for the complete framer register list. Register Name: RHC Register Description: Receive HDLC Control Register Register Address: 010h + (200h 1)) + (2000h x [(n - ...
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Register Name: RHBSE Register Description: Receive HDLC Bit Suppress Register Register Address: 011h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name BSE8 BSE7 ...
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Register Name: RDS0SEL Register Description: Receive Channel Monitor Select Register Register Address: 012h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name — — ...
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Register Name: T1RCR2 (T1 Mode) Register Description: Receive Control Register 2 Register Address: 014h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name — ...
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Register Name: E1RSAIMR (E1 Mode Only) Register Description: Receive Sa Bit Interrupt Mask Register Register Address: 014h + (200h 1)) + (2000h x [( 8]): where Bit # 7 ...
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Register Name: T1RBOCC (T1 Mode Only) Register Description: Receive BOC Control Register Register Address: 015h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name ...
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Register Name: T1RSAOI1, T1RSAOI2, T1RSAOI3 (T1 Mode Only) Register Description: Receive-Signaling All-Ones Insertion Registers Register Address: 038h, 039h, 03Ah + (200h 1)) + (2000h x [( 8]): where ...
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Register Name: RS1 to RS16 Register Description: Receive-Signaling Registers Register Address: 040h to 04Fh + (200h 1)) + (2000h x [( 8]): where Mode: (MSB) ...
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Register Name: LCVCR1 Register Description: Line Code Violation Count Register 1 Register Address: 050h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name LCVC15 ...
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Register Name: FOSCR1 Register Description: Frames Out of Sync Count Register 1 Register Address: 054h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name FEACR15 FEACR14 Default 0 0 Bits Error Count A Register 1 Bits (FEACR[15:8]). FEACR15 is the MSB of the 16-bit Far End A ...
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Register Name: RDS0M Register Description: Receive DS0 Monitor Register Register Address: 060h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name B1 B2 Default ...
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Register Name: T1RFDL (T1 Mode) Register Description: Receive FDL Register Register Address: 062h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name RFDL7 RFDL6 ...
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Register Name: T1RBOC (T1 Mode) Register Description: Receive BOC Register Register Address: 63h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name — — ...
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Register Name: T1RSLC1, T1RSLC2, T1RSLC3 (T1 Mode) Register Description: Receive SLC96 Data Link Registers Register Address: 064h, 065h, 066h + (200h 1)) + (2000h x [( 8]): where (MSB) ...
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Register Name: E1RNAF (E1 Mode) Register Description: E1 Receive Non-Align Frame Register Register Address: 065h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name ...
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Register Name: E1RSiNAF (E1 Mode Only) Register Description: Receive Si Bits of the Non-Align Frame Register Register Address: 067h + (200h 1)) + (2000h x [( 8]): where Bit ...
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Register Name: E1RSa4 (E1 Mode Only) Register Description: Received Sa4 Bits Register Register Address: 069h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name ...
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Register Name: E1RSa6 (E1 Mode Only) Register Description: Received Sa6 Bits Register Register Address: 06Bh + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name ...
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Register Name: E1RSa8 (E1 Mode Only) Register Description: Received Sa8 Bits Register Register Address: 06Dh + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name ...
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Register Name: Sa6CODE Register Description: Received Sa6 Codeword Register Register Address: 06Fh + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name — — Default ...
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Register Name: RCR1 (T1 Mode) Register Description: Receive Control Register 1 Register Address: 081h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name SYNCT ...
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Register Name: RCR1 (E1 Mode) Register Description: Receive Control Register 1 Register Address: 081h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name — ...
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Register Name: T1RIBCC (T1 Mode) Register Description: Receive In-Band Code Control Register Register Address: 082h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name ...
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Register Name: RCR3 Register Description: Receive Control Register 3 Register Address: 083h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name — uALAW Default ...
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Register Name: E1RDMWE1, E1RDMWE2, E1RDMWE3, E1RDMWE4 Register Description: E1 Receive Digital Milliwatt Enable Registers Register Address: 000h, 001h, 002h, 003h + (200h 1)) + (2000h x [( 8]): where n = ...
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Register Name: RIOCR Register Description: Receive I/O Configuration Register Register Address: 084h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name RCLKINV RSYNCINV RCLKINV ...
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Register Name: RESCR Register Description: Receive Elastic Store Control Register Register Address: 085h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name RDATFMT RGCLKEN ...
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Register Name: ERCNT Register Description: Error Counter Configuration Register Register Address: 086h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name 1SECS MCUS 1SECS ...
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Register Name: RHFC Register Description: Receive HDLC FIFO Control Register Register Address: 087h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name — — ...
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Register Name: T1RSCC (T1 Mode Only) Register Description: In-Band Receive Spare Control Register Register Address: 089h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 ...
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Register Name: RBPBS Register Description: Receive BERT Port Bit Suppress Register Register Address: 08Bh + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name BPBSE8 ...
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Register Name: RLS1 Register Description: Receive Latched Status Register 1 Register Address: 090h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name RRAIC RAISC ...
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Register Name: RLS2 (T1 Mode) Register Description: Receive Latched Status Register 2 Register Address: 091h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name ...
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Register Name: RLS3 (T1 Mode) Register Description: Receive Latched Status Register 3 Register Address: 092h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name ...
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Register Name: RLS3 (E1 Mode) Register Description: Receive Latched Status Register 3 Register Address: 092h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name ...
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Register Name: RLS4 Register Description: Receive Latched Status Register 4 Register Address: 093h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name RESF RESEM ...
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Register Name: RLS5 Register Description: Receive Latched Status Register 5 (HDLC) Register Address: 094h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name — ...
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Register Name: RLS7 (T1 Mode) Register Description: Receive Latched Status Register 7 Register Address: 096h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name ...
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Register Name: RSS1, RSS2, RSS3, RSS4 Register Description: Receive-Signaling Status Registers Register Address: 098h, 099h, 09Ah, 09Bh + (200h 1)) + (2000h x [( 8]): where ...
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Register Name: T1RSCD1 (T1 Mode Only) Register Description: Receive Spare Code Definition Register 1 Register Address: 09Ch + (200h 1)) + (2000h x [( 8]): where Bit # 7 ...
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Register Name: RIIR Register Description: Receive Interrupt Information Register Register Address: 9Fh + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name — RLS7 Default ...
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Register Name: RIM2 (E1 Mode Only) Register Description: E1 Receive Interrupt Mask Register 2 Register Address: 0A1h + (200h 1)) + (2000h x [( 8]): where Bit # 7 ...
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Register Name: RIM3 (T1 Mode) Register Description: Receive Interrupt Mask Register 3 Register Address: 0A2h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 Name ...
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Register Name: RIM3 (E1 Mode) Register Description: E1 Receive Interrupt Mask Register 3 Register Address: 0A2h + (200h 1)) + (2000h x [( 8]): where Bit # 7 6 ...