DS26519GN+ Maxim Integrated Products, DS26519GN+ Datasheet - Page 11

• Manufacturer Part Number: DS26519GN+
• Description: IC TXRX T1/E1/J1 16PRT 484-HSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26519GN+

• Number Of Drivers/receivers: 16/16
• Protocol: Ethernet
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 484-BGA Exposed Pad, 484-eBGA, 484-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.5
2.6
Framer/Formatter
Fully independent transmit and receive functionality
Full receive and transmit path transparency
T1 framing formats D4 and ESF per T1.403 and expanded SLC-96 support (TR-TSY-008)
E1 FAS framing and CRC-4 multiframe per G.704/G.706, and G.732 CAS multiframe
Transmit-side synchronizer
Transmit midpath CRC recalculate (E1)
Detailed alarm and status reporting with optional interrupt support
Large path and line error counters
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DS1 Idle Code Generation on a per-channel basis in both transmit and receive paths
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−
ANSI T1.403-1999 support
G.965 V5.2 link detect
Ability to monitor one DS0 channel in both the transmit and receive paths
In-band repeating pattern generators and detectors
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−
Bit oriented code (BOC) support
Flexible signaling support
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−
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−
Automatic RAI generation to ETS 300 011 specifications
RAI-CI and AIS-CI support
Expanded access to Sa and Si bits
Option to extend carrier loss criteria to a 1ms period as per ETS 300 233
Japanese J1 support
Ability to calculate and check CRC-6 according to the Japanese standard
Ability to generate Yellow Alarm according to the Japanese standard
T1-to-E1 conversion
System Interface
Independent two-frame receive and transmit elastic stores
Independent control and clocking
Controlled slip capability with status
Minimum delay mode supported
Flexible TDM backplane supports bus rates from 1.544MHz to 16.384MHz
Supports T1 to CEPT (E1) conversion
Programmable output clocks for fractional T1, E1, H0, and H12 applications
Interleaving PCM bus operation
Hardware signaling capability
Receive signaling reinsertion to a backplane multiframe sync
Availability of signaling in a separate PCM data stream
T1: BPV, CV, CRC-6, and framing bit errors
E1: BPV, CV, CRC-4, E-bit, and frame alignment errors
Timed or manual update modes
User defined
Digital Milliwatt
Three independent generators and detectors
Patterns from 1 to 8 bits or 16 bits in length
Software or hardware based
Interrupt generated on change of signaling data
Optional receive signaling freeze on loss of frame, loss of signal, or frame slip
Hardware pins provided to indicate loss of frame (LOF), loss of signal (LOS), loss of transmit clock
(LOTC), or signaling freeze condition
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DS26519 16-Port T1/E1/J1 Transceiver