WJLXT972ALC.A4 Intel, WJLXT972ALC.A4 Datasheet - Page 21

• Manufacturer Part Number: WJLXT972ALC.A4
• Description: IC TRANS 3.3V ETHERNET 64-LQFP
• Manufacturer: Intel
• Type: Transceiverr

Specifications of WJLXT972ALC.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 857341

LXT972M PHY
Datasheet
302875, Revision 5.3
31 October 2007
5.0
5.1
5.1.1
5.1.2
Cortina Systems
Functional Description
This chapter has the following sections:
Device Overview
The LXT972M PHY is a single-port Fast Ethernet 10/100 PHY that supports 10 Mbps and
100 Mbps networks. It complies with applicable requirements of IEEE 802.3. It directly
drives either a 100BASE-TX line or a 10BASE-T line.
Comprehensive Functionality
The LXT972M PHY provides a standard Media Independent Interface (MII) for 10/100
MACs. The LXT972M PHY performs all functions of the Physical Coding Sublayer (PCS)
and Physical Media Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X
standard. It also performs all functions of the Physical Media Dependent (PMD) sublayer
for 100BASE-TX connections.
If the LXT972M PHY is not set for forced operation, it uses auto-negotiation/parallel
detection to automatically determine line operating conditions. If the PHY device on the
other side of the link supports auto-negotiation, the LXT972M PHY auto-negotiates with it
using Fast Link Pulse (FLP) Bursts. If the PHY partner does not support auto-negotiation,
the LXT972M PHY automatically detects the presence of either link pulses (10 Mbps
PHY) or Idle symbols (100 Mbps PHY) and sets its operating conditions accordingly.
The LXT972M PHY provides half-duplex and full-duplex operation at 100 Mbps and
10 Mbps.
Optimal Signal Processing Architecture
The LXT972M PHY incorporates high-efficiency Optimal Signal Processing (OSP) design
techniques, which combine optimal properties of digital and analog signal processing.
The receiver utilizes decision feedback equalization to increase noise and cross-talk
immunity by as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal
processing techniques in the receive equalizer avoids the quantization noise and
calculation truncation errors found in traditional DSP-based receivers (typically complex
DSP engines with A/D converters). This results in improved receiver noise and cross-talk
performance.
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LXT972M Single-Port 10/100 Mbps PHY Transceiver
Section 5.1, Device Overview, on page 21
Section 5.2, Network Media / Protocol Support, on page 22
Section 5.3, Operating Requirements, on page 25
Section 5.4, Initialization, on page 25
Section 5.5, Establishing Link, on page 28
Section 5.6, MII Operation, on page 30
Section 5.7, 100 Mbps Operation, on page 35
Section 5.8, 10 Mbps Operation, on page 42
Section 5.9, Monitoring Operations, on page 43
Section 5.10, Boundary Scan (JTAG 1149.1) Functions, on page 45
5.0 Functional Description
Page 21