WJLXT972ALC.A4 Intel, WJLXT972ALC.A4 Datasheet - Page 46

• Manufacturer Part Number: WJLXT972ALC.A4
• Description: IC TRANS 3.3V ETHERNET 64-LQFP
• Manufacturer: Intel
• Type: Transceiverr

Specifications of WJLXT972ALC.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 857341

LXT972M PHY
Datasheet
302875, Revision 5.3
31 October 2007
5.10.4
Table 17
5.10.5
Table 18
Cortina Systems
Boundary Scan Register
Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used
for the serial shift stage and the parallel output stage.
operation.
BSR Mode of Operation
Device ID Register
Table 18
continuation characters, see the specification update for the LXT972M PHY.
Device ID Register
®
1. The JEDEC ID is an 8-bit identifier. The MSB is for parity and is ignored. The JEDEC ID is FE
Bits 31:28
Mode
LXT972M Single-Port 10/100 Mbps PHY Transceiver
Version
1
2
3
4
XXXX
(1111 1110), which becomes 111 1110.
lists the bits for the Device ID register. For the current version of the JEDEC
Part ID (Hex)
System Function
Bits 27:12
Description
03CB
Capture
Update
Shift
JEDEC Continuation Characters
Bits 11:8
0000
Table 17
lists the four BSR modes of
5.10 Boundary Scan (JTAG
JEDEC ID
111 1110
Bits 7:1
1149.1) Functions
1
Reserved
Bit 0
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