SAB-C161PI-L25F CA Infineon Technologies, SAB-C161PI-L25F CA Datasheet - Page 47
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SAB-C161PI-L25F CA
Manufacturer Part Number
SAB-C161PI-L25F CA
Description
Microcontrollers (MCU) 16BIT SNGL CHIP 5V 25MHz ROM less
Manufacturer
Infineon Technologies
Datasheet
1.SAB-C161PI-L25F_CA.pdf
(82 pages)
Specifications of SAB-C161PI-L25F CA
Data Bus Width
16 bit
Program Memory Type
ROMLess
Data Ram Size
3 KB
Interface Type
ASC, I2C, SSC
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
76
Number Of Timers
5
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
TQFP-100
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 4 Channel
Packages
PG-TQFP-100
Max Clock Frequency
25.0 MHz
Sram (incl. Cache)
3.0 KByte
A / D Input Lines (incl. Fadc)
4
Program Memory
0.0 KByte
Lead Free Status / Rohs Status
Details
Other names
B161PIL25FCAXT
AC Characteristics
Definition of Internal Timing
The internal operation of the C161PI is controlled by the internal CPU clock f
edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)
operations.
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see figure below).
Figure 11
The CPU clock signal
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate
be regarded when calculating the timings for the C161PI.
Note: The example for PLL operation shown in the fig. above refers to a PLL factor of 4.
The used mechanism to generate the CPU clock is selected during reset via the logic
levels on pins P0.15-13 (P0H.7-5).
The table below associates the combinations of these three bits with the respective clock
generation mode.
Data Sheet
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Generation Mechanisms for the CPU Clock
CPU
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TCL
CPU
. This influence must
TCL
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TCL TCL
CPU
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