AD1896AYRSZ Analog Devices Inc, AD1896AYRSZ Datasheet - Page 20

• Manufacturer Part Number: AD1896AYRSZ
• Description: IC CONV SAMPLE RATE ASYNC 28SSOP
• Manufacturer: Analog Devices Inc
• Type: Sample Rate Converterr

Specifications of AD1896AYRSZ

• Applications: Automotive Audio, processing, receivers
• Voltage - Supply, Digital: 3.13 V ~ 3.46 V
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Audio Control Type: Sample Rate Converter
• Output Power: 132mW
• Supply Voltage Range: 3.135V To 3.465V, 3.135V To 5.5V
• Operating Temperature Range: -40°C To +105°C
• Audio Ic Case Style: SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD1896
The digital servo loop is essentially a ramp filter that provides
the initial pointer to the address in RAM and ROM for the start
of the FIR convolution. The RAM pointer is the integer output
of the ramp filter while the ROM is the fractional part. The
digital servo loop must be able to provide excellent rejection of
jitter on the f
of the f
also divide the fractional part of the ramp output by the ratio of
f
the ROM coefficients.
The digital servo loop is implemented with a multirate filter. To
settle the digital servo loop filter quicker upon start-up or a change
in the sample rate, a “fast mode” was added to the filter. When
the digital servo loop starts up or the sample rate is changed, the
digital servo loop kicks into “fast mode” to adjust and settle
on the new sample rate. Upon sensing the digital servo loop
settling down to some reasonable value, the digital servo loop
will kick into “normal” or “slow mode.” During “fast mode”
the MUTE_OUT signal of the sample rate converter is asserted
to let the user know that they should mute the sample rate
converter to avoid any clicks or pops. The frequency response of
the digital servo loop for “fast mode” and “slow mode” are
shown in Figure 8.
S_IN
/f
S_OUT
Figure 8. Frequency Response of the Digital Servo Loop. f
Frequency Is 30 MHz.
S_OUT
for the case when f
S_IN
clock within 4.97 ps. The digital servo loop will
and f
S_OUT
–100
–110
–120
–130
–140
–150
–160
–170
–180
–190
–200
–210
–220
–10
–20
–30
–40
–50
–60
–70
–80
–90
10
0
0.01
clocks as well as measure the arrival
S_IN
> f
S_OUT
0.1
, to dynamically alter
1
SLOW MODE
10
FREQUENCY – Hz
–20–
The FIR filter is a 64-tap filter in the case of f
(f
filter performs its convolution by loading in the starting address
of the RAM address pointer and the ROM address pointer
from the digital servo loop at the start of the f
The FIR filter then steps through the RAM by decrementing its
address by 1 for each tap, and the ROM pointer increments its
address by the (f
for f
volution is completed. The convolution is performed for both
the left and right channels, and the multiply accumulate circuit
used for the convolution is shared between the channels.
The f
alter the coefficients in the ROM for the case when f
f
f
f
ratio is updated if it is different by more than two f
from the previous f
provide some hysteresis to prevent the filter length from oscillat-
ing and causing distortion.
S_OUT
S_OUT
S_IN
S_IN
S_IN
S_OUT
100
, the ratio is held at one. If f
/f
Is the X-Axis, f
S_IN
. The ratio is calculated by comparing the output of an
S_OUT
counter to the output of an f
/f
FAST MODE
≥ f
S_OUT
) ¥ 64 taps for the case when f
S_IN
1e3
. Once the ROM address rolls over, the con-
S_OUT
sample rate ratio circuit is used to dynamically
S_OUT
S_OUT
/f
S_IN
to f
) ¥ 2
1e4
= 192 kHz, Master Clock
S_IN
20
S_IN
ratio for f
comparison. This is done to
S_IN
> f
1e5
S_OUT
S_IN
counter. If f
S_OUT
S_IN
> f
, the sample rate
S_OUT
> f
S_OUT
≥ f
S_OUT
S_OUT
S_IN
period.
. The FIR
S_OUT
S_IN
and is
REV. A
periods
or 2
>
>
20