AD1896AYRSZ Analog Devices Inc, AD1896AYRSZ Datasheet - Page 23

• Manufacturer Part Number: AD1896AYRSZ
• Description: IC CONV SAMPLE RATE ASYNC 28SSOP
• Manufacturer: Analog Devices Inc
• Type: Sample Rate Converterr

Specifications of AD1896AYRSZ

• Applications: Automotive Audio, processing, receivers
• Voltage - Supply, Digital: 3.13 V ~ 3.46 V
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Audio Control Type: Sample Rate Converter
• Output Power: 132mW
• Supply Voltage Range: 3.135V To 3.465V, 3.135V To 5.5V
• Operating Temperature Range: -40°C To +105°C
• Audio Ic Case Style: SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. A
TDM MODE APPLICATION
In TDM mode, several AD1896s can be daisy-chained together
and connected to the serial input port of a SHARC DSP. The
AD1896 contains a 64-bit parallel load shift register. When the
LRCLK_O pulse arrives, each AD1896 parallel loads its left and
right data into the 64-bit shift register. The input to the shift
register is connected to TDM_IN, while the output is connected
to SDATA_O. By connecting the SDATA_O to the TDM_IN
LRCLK
SCLK
LRCLK
LRCLK
LRCLK
LRCLK
SDATA
SDATA
SDATA
SDATA
TDM_IN
SCLK
SCLK
SCLK
SCLK
M2
PHASE-MASTER
0
NOTES
1
2
3
LRCLK NORMALLY OPERATES AT ASSOCIATIVE INPUT OR OUTPUT SAMPLE FREQUENCY (f
SCLK FREQUENCY IS NORMALLY 64
WHERE N = NUMBER OF STEREO CHANNELS IN THE TDM CHAIN, IN MASTER MODE N = 4.
PLEASE NOTE THAT 8 BITS OF EACH 32-BIT SUBFRAME ARE USED FOR TRANSMITTING
AD1896
MATCHED-PHASE MODE DATA. PLEASE REFER TO FIGURE 14.
Figure 11. Daisy-Chain Configuration for TDM Mode (All AD1896s Being Clock-Slaves)
M1
0
MSB
MSB
LRCLK_O
SDATA_O
SCLK_O
M0
0
MSB
MSB
MSB
LEFT CHANNEL
LEFT CHANNEL
LEFT CHANNEL
Figure 10. Input/Output Serial Data Formats
LEFT-JUSTIFIED MODE – 16 BITS TO 24 BITS PER CHANNEL
RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL
TDM MODE – 16 BITS TO 24 BITS PER CHANNEL
TDM_IN
I
2
S MODE – 16 BITS TO 24 BITS PER CHANNEL
M2
LRCLK EXCEPT FOR TDM MODE WHICH IS N
0
1
AD1896
SLAVE-1
LSB
M1
0
0
LRCLK_O
SDATA_O
SCLK_O
LSB
LSB
M0
0
0
LSB
–23–
1/f
of the next AD1896, a large shift register is created, which is
clocked by SCLK_O.
The number of AD1896s that can be daisy-chained together is
limited by the maximum frequency of SCLK_O, which is about
25 MHz. For example, if the output sample rate, f
up to eight AD1896s could be connected since 512 ¥ f
than 25 MHz. In master/TDM mode, the number of AD1896s
that can be daisy-chained is fixed to four.
MSB
MSB
s
TDM_IN
MSB
MSB
MSB
M2
0
1
AD1896
SLAVE-n
64
M1
MSB
0
0
LRCLK_O
SDATA_O
f
s
SCLK_O
s
RIGHT CHANNEL
RIGHT CHANNEL
RIGHT CHANNEL
,
).
M0
0
0
LSB
STANDARD MODE
MATCHED-PHASE MODE
LSB
LSB
DR0
RFS0
RCLK0
LSB
SHARC
DSP
AD1896
S
, is 48 kHz,
S
is less