AD1896AYRSZ Analog Devices Inc, AD1896AYRSZ Datasheet - Page 21

• Manufacturer Part Number: AD1896AYRSZ
• Description: IC CONV SAMPLE RATE ASYNC 28SSOP
• Manufacturer: Analog Devices Inc
• Type: Sample Rate Converterr

Specifications of AD1896AYRSZ

• Applications: Automotive Audio, processing, receivers
• Voltage - Supply, Digital: 3.13 V ~ 3.46 V
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Audio Control Type: Sample Rate Converter
• Output Power: 132mW
• Supply Voltage Range: 3.135V To 3.465V, 3.135V To 5.5V
• Operating Temperature Range: -40°C To +105°C
• Audio Ic Case Style: SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

However, the hysteresis of the f
phase mismatching between two AD1896s operating with the
same input clock and the same output clock. Since the hyster-
esis requires a difference of more than two f
f
ferences in their ratios from 0 to 4 f
f
corresponds directly with the group delay. Thus, the magnitude
in the phase difference will depend upon the resolution of the
f
counters, the smaller the phase difference error will be.
The f
extra resolution over the AD1890, which reduces the phase
mismatch error by a factor of 8. However, an additional feature
was added to the AD1896 to eliminate the phase mismatching
completely. One AD1896 can set the f
AD1896s by transmitting its f
serial output port.
OPERATING FEATURES
RESET and Power-Down
When RESET is asserted low, the AD1896 will turn off the
master clock input to the AD1896, MCLK_I, initialize all of its
internal registers to their default values, and three-state all of the
I/O pins. While RESET is active low, the AD1896 is consuming
minimum power. For the lowest possible power consumption
while RESET is active low, all of the input pins to the AD1896
should be static.
When RESET is deasserted, the AD1896 begins its initialization
routine where all locations in the FIFO are initialized to zero,
MUTE_OUT is asserted high, and any I/O pins configured as
outputs are enabled. When RESET is deasserted, the master
serial port clock pins SCLK_I/O and LRCLK_I/O become
active after 1024 MCLK-I cycles. The mute control counter,
which controls the soft mute attenuation of the input samples,
is initialized to maximum attenuation, –144 dB (see the Mute
Control section).
When asserting RESET and deasserting RESET, the RESET
should be held low for a minimum of five MCLK_I cycles.
During power-up, the RESET should be held low until the
power supplies have stabilized. It is recommended that the
AD1896 be reset when changing modes.
Power Supply and Voltage Reference
The AD1896 is designed for 3 V operation with 5 V input toler-
ance on the input pins. VDD_CORE is the 3 V supply that is
used to power the core logic of the AD1896 and to drive the
output pins. VDD_IO is used to set the input voltage tolerance
of the input pins. In order for the input pins to be 5 V input
tolerant, VDD_IO must be connected to a 5 V supply. If the
input pins do not have to be 5 V input tolerant, then
VDD_IO can be connected to VDD_CORE. VDD_IO should
never be less than VDD_CORE. VDD_CORE and VDD_IO
should be bypassed with 100 nF ceramic chip capacitors, as
close to the pins as possible, to minimize power supply and
ground bounce caused by inductance in the traces. A bulk alu-
minium electrolytic capacitor of 47 mF should also be provided
on the same PC board as the AD1896.
REV. A
S_OUT
S_OUT
S_OUT
S_IN
/f
/f
and f
S_IN
S_IN
and f
ratio adjusts the filter length of the AD1896, which
ratio to be updated, two AD1896s may have dif-
S_IN
S_OUT
counters. The greater the resolution of the
counters of the AD1896 have three bits of
S_OUT
S_OUT
/f
/f
S_OUT
S_IN
S_IN
S_OUT
ratio through the
ratio circuit can cause
period counts. The
S_OUT
/f
S_IN
ratio of other
periods for the
–21–
Digital Filter Group Delay
The group delay of the digital filter may be selected by the logic
pin GRPDLYS. As mentioned in the Theory of Operation section,
this pin is particularly useful in varispeed applications. The
GRPDLYS pin has an internal pull-up resistor of approximately
33 kW to VDD_CORE. When GRPDLYS is high, the filter group
delay will be short and is given by the equation:
For short filter group delay, the GRPDLYS pin can be left open.
When GRPDLYS is low, the group delay of the filter will be
long and is given by the equation:
NOTE: For the long group delay mode, the decimation ratio is
limited to less than 7:1.
Mute Control
When the MUTE_IN pin is asserted high, the MUTE_IN control
will perform a soft mute by linearly decreasing the input data to
the AD1896 FIFO to zero, –144 dB attenuation. When MUTE_IN
is deasserted low, the MUTE_IN control will linearly decrease
the attenuation of the input data to 0 dB. A 12-bit counter,
clocked by LRCLK_I, is used to control the mute attenuation.
Therefore, the time it will take from the assertion of MUTE_IN
to –144 dB full mute attenuation is 4096/LRCLK_I seconds.
Likewise, the time it will take to reach 0 dB mute attenuation from
the deassertion of MUTE_IN is 4096/LRCLK_I seconds.
Upon RESET, or a change in the sample rate between LRCLK_I
and LRCLK_O, the MUTE_OUT pin will be asserted high. The
MUTE_OUT pin will remain asserted high until the digital
servo loop’s internal fast settling mode has completed. When
the digital servo loop has switched to slow settling mode, the
MUTE_OUT pin will deassert. While MUTE_OUT is asserted,
the MUTE_IN pin should be asserted as well to prevent any
major distortion in the audio output samples.
Master Clock
A digital clock connected to the MCLK_I pin or a fundamental
or third overtone crystal connected between MCLK_I and
MCLK_O can be used to generate the master clock, MCLK_I.
The MCLK_I pin can be 5 V input tolerant just like any of the
other AD1896 input pins. A fundamental mode crystal can be
inserted between MCLK_I and MCLK_O for master clock
frequency generation up to 27 MHz. For master clock fre-
quency generation with a crystal beyond 27 MHz, it is
recommended that the user use a third overtone crystal and to
add an LC filter at the output of MCLK_O to filter out the
fundamental, do not notch filter the fundamental. Please refer
to your quartz crystal supplier for values for external capaci-
tors and inductor components.
GDL
GDL
GDS
GDS
=
=
=
=
f
f
f
f
S_IN
S_IN
16
S_IN
16
S_IN
64
64
+
+
+
+
Ê
Á
Ë
Ê
Á
Ë
f
f
S_IN
S_IN
32
32
f
f
S_IN
S_IN
32
32
seconds
seconds
ˆ
˜ ¥
¯
ˆ
˜ ¥
¯
Ê
Á
Ë
Ê
Á
Ë
f
f
S_OUT
S_OUT
f
f
S_IN
S_IN
for f
for f
S_OUT
S_OUT
ˆ
˜
¯
ˆ
˜
¯
seconds
seconds
>
>
f
f
S_IN
S_IN
for f
for f
AD1896
S_OUT
S_OUT
<
<
f
f
S_IN
S_IN