AD1895AYRSRL Analog Devices Inc, AD1895AYRSRL Datasheet - Page 18

• Manufacturer Part Number: AD1895AYRSRL
• Description: IC SAMP-RATEHP/CONV 24BIT 28SSOP
• Manufacturer: Analog Devices Inc
• Type: Sample Rate Converterr

Specifications of AD1895AYRSRL

• Rohs Status: RoHS non-compliant
• Applications: Automotive Audio, receivers, set-top boxes
• Voltage - Supply, Digital: 3.13 V ~ 3.46 V
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• For Use With: EVAL-AD1895EB - BOARD EVAL FOR AD1895
• Voltage - Supply, Analog: -
• Lead Free Status / RoHS Status: Not Compliant

AD1895
The digital servo loop is essentially a ramp filter that provides
the initial pointer to the address in RAM and ROM for the start
of the FIR convolution. The RAM pointer is the integer output
of the ramp filter, while the ROM is the fractional part. The
digital servo loop must be able to provide excellent rejection of
jitter on the f
of the f
also divide the fractional part of the ramp output by the ratio of
f
the ROM coefficients.
The digital servo loop is implemented with a multirate filter. To
settle the digital servo loop filter quicker upon startup or a change
in the sample rate, a Fast Mode was added to the filter. When
the digital servo loop starts up or the sample rate is changed, the
digital servo loop kicks into Fast Mode to adjust and settle on the
new sample rate. Upon sensing the digital servo loop settling down
to some reasonable value, the digital servo loop will kick into
Normal or Slow Mode. During Fast Mode, the MUTE_OUT
signal of the sample rate converter is asserted to let the user
know that they should mute the sample rate converter to avoid
any clicks or pops. The frequency response of the digital servo
loop for Fast Mode and Slow Mode are shown in Figure 8.
S_IN
/f
S_OUT
Figure 8. Frequency Response of the Digital Servo Loop. f
frequency is 30 MHz.
S_OUT
for the case when f
S_IN
clock within 4.97 ps. The digital servo loop will
and f
S_OUT
–100
–110
–120
–130
–140
–150
–160
–170
–180
–190
–200
–210
–220
–10
–20
–30
–40
–50
–60
–70
–80
–90
10
0
0.01
clocks as well as measure the arrival
S_IN
> f
S_OUT
0.1
, to dynamically alter
1
SLOW MODE
10
FREQUENCY – Hz
–18–
The FIR filter is a 64-tap filter in the case of f
(f
filter performs its convolution by loading in the starting address
of the RAM address pointer and the ROM address pointer
from the digital servo loop at the start of the f
The FIR filter then steps through the RAM by decrementing its
address by 1 for each tap, and the ROM pointer increments its
address by the (f
for f
volution is completed. The convolution is performed for both
the left and right channels, and the multiply accumulate circuit
used for the convolution is shared between the channels.
The f
alter the coefficients in the ROM for the case when f
The ratio is calculated by comparing the output of an f
counter to the output of an f
ratio is held at 1. If f
if it is different by more than two f
f
hysteresis to prevent the filter length from oscillating and causing
distortion.
S_OUT
S_IN
S_IN
S_OUT
100
/f
is the x-axis, f
S_IN
S_OUT
to f
FAST MODE
/f
≥ f
S_OUT
S_IN
) × 64 taps for the case when f
S_IN
comparison. This is done to provide some
1e3
. Once the ROM address rolls over, the con-
S_OUT
sample rate ratio circuit is used to dynamically
S_IN
S_OUT
/f
S_IN
> f
= 192 kHz, master clock
) × 2
S_OUT
1e4
S_IN
20
, the sample rate ratio is updated
counter. If f
S_OUT
ratio for f
1e5
periods from the previous
S_IN
S_OUT
S_IN
S_OUT
> f
S_OUT
> f
S_OUT
≥ f
S_IN
> f
S_OUT
S_IN
S_IN
period.
. The FIR
> f
S_OUT
and is
REV. B
or 2
, the
S_OUT
20
.