AD1895AYRSRL Analog Devices Inc, AD1895AYRSRL Datasheet - Page 20

• Manufacturer Part Number: AD1895AYRSRL
• Description: IC SAMP-RATEHP/CONV 24BIT 28SSOP
• Manufacturer: Analog Devices Inc
• Type: Sample Rate Converterr

Specifications of AD1895AYRSRL

• Rohs Status: RoHS non-compliant
• Applications: Automotive Audio, receivers, set-top boxes
• Voltage - Supply, Digital: 3.13 V ~ 3.46 V
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• For Use With: EVAL-AD1895EB - BOARD EVAL FOR AD1895
• Voltage - Supply, Analog: -
• Lead Free Status / RoHS Status: Not Compliant

AD1895
Serial Data Ports—Data Format
The Serial Data Input Port Mode is set by the logic levels on the
SMODE_IN_0/SMODE_IN_1/SMODE_IN_2 pins. The serial
data input port modes available are left justified, I
justified (RJ), 16, 18, 20, or 24 bits, as defined in Table I.
2
0
0
0
0
1
1
1
1
The Serial Data Output Port Mode is set by the logic levels on the
SMODE_OUT_0/SMODE_OUT_1 and WLNGTH_OUT_0/
WLNGTH_OUT_1 pins. The serial mode can be changed to left
justified, I
output word width can be set by using the WLNGTH_OUT_0/
WLNGTH_OUT_1 pins as shown in
SMODE_IN_[0:2]
2
S, right justified, or TDM as defined in the Table II. The
1
0
0
1
1
0
0
1
1
Table I. Serial Data Input Port Mode
LRCLK
LRCLK
LRCLK
LRCLK
SDATA
SDATA
SDATA
SDATA
SCLK
SCLK
SCLK
SCLK
NOTES
1. LRCLK NORMALLY OPERATES AT ASSOCIATIVE INPUT OR OUTPUT SAMPLE FREQUENCY (
2. SCLK FREQUENCY IS NORMALLY 64
WHERE N = NUMBER OF STEREO CHANNELS IN THE TDM CHAIN. IN MASTER MODE, N = 4
MSB
0
0
1
0
1
0
1
0
1
MSB
MSB
MSB
Interface Format
Left Justified
I
Undefined
Undefined
Right Justified, 16 Bits
Right Justified, 18 Bits
Right Justified, 20 Bits
Right Justified, 24 Bits
2
S
MSB
LEFT CHANNEL
LEFT CHANNEL
LEFT CHANNEL
Figure 10. Input/Output Serial Data Formats
LEFT-JUSTIFIED MODE – 16 BITS TO 24 BITS PER CHANNEL
I
RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL
TDM MODE – 16 BITS TO 24 BITS PER CHANNEL
2
S MODE – 16 BITS TO 24 BITS PER CHANNEL
LRCLK EXCEPT FOR TDM MODE, WHICH IS N
2
S, and right
LSB
LSB
LSB
–20–
LSB
1/
Table III. When the output word width is less than 24 bits, dither is
added to the truncated bits. The Right-Justified Serial Data Out
Mode assumes 64 SCLK_O cycles per frame, divided evenly
for left and right. The AD1895 also supports 16-bit, 32-clock
packed input and output serial data in LJ, RJ, and I
SMODE_OUT_[0:2]
1
0
0
1
1
WLNGTH_OUT_[0:1]
1
0
0
1
1
The following timing diagrams show the serial mode formats.
f
MSB
MSB
s
MSB
MSB
MSB
Table II. Serial Data Output Port Mode
64
MSB
0
0
1
0
1
0
0
1
0
1
f
RIGHT CHANNEL
RIGHT CHANNEL
RIGHT CHANNEL
f
s
s
,
)
Table III. Word Width
Interface Format
Left Justified (LJ)
I
TDM Mode
Right Justified (RJ)
Word Width
24 Bits
20 Bits
18 Bits
16 Bits
LSB
2
S
LSB
LSB
LSB
2
S format.
REV. B