AD1895AYRSRL Analog Devices Inc, AD1895AYRSRL Datasheet - Page 22

• Manufacturer Part Number: AD1895AYRSRL
• Description: IC SAMP-RATEHP/CONV 24BIT 28SSOP
• Manufacturer: Analog Devices Inc
• Type: Sample Rate Converterr

Specifications of AD1895AYRSRL

• Rohs Status: RoHS non-compliant
• Applications: Automotive Audio, receivers, set-top boxes
• Voltage - Supply, Digital: 3.13 V ~ 3.46 V
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• For Use With: EVAL-AD1895EB - BOARD EVAL FOR AD1895
• Voltage - Supply, Analog: -
• Lead Free Status / RoHS Status: Not Compliant

AD1895
Serial Data Port Master Clock Modes
Either of the AD1895 serial ports can be configured as a
master serial data port. However, only one serial port can be
a master, while the other has to be a slave. In Master Mode, the
AD1895 requires a 256 × f
(MCLK_IN). For a maximum master clock frequency of 30 MHz,
the maximum sample rate is limited to 96 kHz. In Slave Mode,
sample rates up to 192 kHz can be handled.
When either of the serial ports is operated in Master Mode, the
master clock is divided down to derive the associated left/right
subframe clock (LRCLK) and serial bit clock (SCLK). The master
clock frequency can be selected for 256, 512, or 768 times the
input or output sample rate. Both the input and output serial
ports will support Master Mode LRCLK and SCLK generation
for all serial modes, left justified, I
for the output serial port.
S
, 512 f
S
2
, or 768 × f
S, right justified, and TDM
S
master clock
–22–
MMODE_0/
MMODE_1/
MMODE_2
2
0
0
0
0
1
1
1
1
Bypass Mode
When the BYPASS pin is asserted high, the input data bypasses
the sample rate converter and is sent directly to the serial output
port. Dithering of the output data when the word length is set
to less than 24 bits is disabled. This mode is ideal when the
input and output sample rates are the same and LRCLK_I and
LRCLK_O are synchronous with respect to each other. This
mode can also be used for passing through nonaudio data,
since no processing is performed on the input data in this mode.
1
0
0
1
1
0
0
1
1
Table IV. Serial Data Port Clock Modes
0
0
1
0
1
0
1
0
1
Interface Format
Both Serial Ports Are in Slave Mode
Output Serial Port Is Master with 768 × f
Output Serial Port Is Master with 512 × f
Output Serial Port Is Master with 256 × f
Undefined
Input Serial Port Is Master with 768 × f
Input Serial Port Is Master with 512 × f
Input Serial Port Is Master with 256 × f
REV. B
S_OUT
S_OUT
S_OUT
S_IN
S_IN
S_IN