ADV7181BCP Analog Devices Inc, ADV7181BCP Datasheet - Page 16

• Manufacturer Part Number: ADV7181BCP
• Description: IC VIDEO DECODER NTSC 64-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7181BCP

• Applications: Recorders, Set-Top Boxes
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Adc/dac Resolution: 9b
• Screening Level: Industrial
• Package Type: LFCSP EP
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-ADV7181BEB - BOARD EVALUATION FOR ADV7181
• Lead Free Status / RoHS Status: Compliant, Contains lead / RoHS non-compliant

ADV7181
GLOBAL PIN CONTROL
Three-State Output Drivers
TOD, Address 0x03 [6]
This bit allows the user to three-state the output drivers of the
ADV7181.
Upon setting the TOD bit, the P15–P0, HS, VS, FIELD, and SFL
pins are three-stated.
The timing pins (HS/VS/FIELD) can be forced active via the
TIM_OE bit. For more information on three-state control, refer
to the following sections:
•
•
Individual drive strength controls are provided via the
DR_STR_XX bits.
Table 16. TOD Function
TOD
0 (default)
1
Three-State LLC Driver
TRI_LLC, Address 0x0E [6]
This bit allows the output drivers for the LLC pin of the
ADV7181 to be three-stated. For more information on three-
state control, refer to the following sections:
•
•
Individual drive strength controls are provided via the
DR_STR_XX bits.
Table 17. TRI_LLC Function
TRI_LLC
0 (default)
1
Three-State LLC Driver
Timing Signals Output Enable
Three-State Output Drivers
Timing Signals Output Enable
Output drivers enabled.
Description
Output drivers three-stated.
Description
LLC pin drivers working according to the
DR_STR_C[1:0] setting (pin enabled).
LLC pin drivers three-stated.
Rev. B | Page 16 of 104
Timing Signals Output Enable
TIM_OE, Address 0x04 [3]
The TIM_OE bit should be regarded as an addition to the TOD
bit. Setting it high forces the output drivers for HS, VS, and
FIELD into the active (that is, driving) state even if the TOD bit
is set. If set to low, the HS, VS, and FIELD pins are three-stated
depending on the TOD bit. This functionality is useful if the
decoder is to be used as a timing generator only. This may be
the case if only the timing signals are to be extracted from an
incoming signal, or if the part is in free-run mode where a
separate chip can output, for instance, a company logo.
For more information on three-state control, refer to the
following sections:
•
•
Individual drive strength controls are provided via the
DR_STR_XX bits.
Table 18. TIM_OE Function
TIM_OE
0 (default)
1
Drive Strength Selection (Data)
DR_STR[1:0] Address 0x04 [5:4]
For EMC and crosstalk reasons, it may be desirable to
strengthen or weaken the drive strength of the output drivers.
The DR_STR[1:0] bits affect the P[15:0] output drivers.
For more information on three-state control, refer to the
following sections:
•
•
Table 19. DR_STR Function
DR_STR[1:0]
00
01 (default)
10
11
Drive Strength Selection (Clock)
Drive Strength Selection (Sync)
Three-State Output Drivers
Three-State LLC Driver
Description
HS, VS, FIELD three-stated according to the
TOD bit.
HS, VS, FIELD are forced active all the time. The
DR_STR_S[1:0] setting determines drive
strength.
Description
Low drive strength (1×).
Medium low drive strength (2×).
Medium high drive strength (3×).
High drive strength (4×).