ADV7181BCP Analog Devices Inc, ADV7181BCP Datasheet - Page 61

• Manufacturer Part Number: ADV7181BCP
• Description: IC VIDEO DECODER NTSC 64-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7181BCP

• Applications: Recorders, Set-Top Boxes
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Adc/dac Resolution: 9b
• Screening Level: Industrial
• Package Type: LFCSP EP
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-ADV7181BEB - BOARD EVALUATION FOR ADV7181
• Lead Free Status / RoHS Status: Compliant, Contains lead / RoHS non-compliant

PIXEL PORT CONFIGURATION
The ADV7181 has a very flexible pixel port that can be config-
ured in a variety of formats to accommodate downstream ICs.
Table 166 and Table 167 summarize the various functions that
the ADV7181’s pins can have in different modes of operation.
The ordering of components, for example, Cr vs. Cb, CHA/B/C,
can be changed. Refer to the SWPC Swap Pixel Cr/Cb, Address
0x27 [7] section. Table 166 indicates the default positions for
the Cr/Cb components.
OF_SEL[3:0] Output Format Selection, Address 0x03 [5:2]
There are several modes in which the ADV7181 pixel port
can be configured. These modes are under the control of
OF_SEL[3:0]. See Table 167 for details.
The default LLC frequency output on the LLC1 pin is approxi-
mately 27 MHz. For modes that operate with a nominal data
rate of 13.5 MHz (0001, 0010), the clock frequency on the LLC1
pin stays at the higher rate of 27 MHz. For information on
outputting the nominal 13.5 MHz clock on the LLC1 pin, see
the LLC1 Output Selection, LLC_PAD_SEL[2:0],
Address 0x8F [6:4] section.
Table 166. P15–P0 Output/Input Pin Mapping
Video Out, 8-Bit, 4:2:2
Video Out, 16-Bit, 4:2:2
Table 167. Standard Definition Pixel Port Modes
OF_SEL[3:0]
0010
0011 (default)
0110-1111
Processor, Format, and Mode
Format
16-Bit @ LLC2 4:2:2
8-Bit @ LLC1 4:2:2
Reserved.
15
14
13
Rev. B | Page 61 of 104
YCrCb[7:0]OUT
Y[7:0]OUT
12
11
SWPC Swap Pixel Cr/Cb, Address 0x27 [7]
This bit allows Cr and Cb samples to be swapped.
Table 164. SWPC Function
SWPC
0 (default)
1
LLC1 Output Selection, LLC_PAD_SEL[2:0],
Address 0x8F [6:4]
The following I
LLC1 (nominally at 27 MHz) and LLC2 (nominally at 13.5 MHz).
The LLC2 signal is useful for LLC2-compatible wide bus
(16-bit) output modes. See the OF_SEL[3:0] Output Format
Selection, Address 0x03 [5:2] section for additional
information. The LLC2 signal and data on the data bus are
synchronized. By default, the rising edge of LLC1/LLC2 is
aligned with the Y data; the falling edge occurs when the data
bus holds C data. The polarity of the clock, and therefore the
Y/C assignments to the clock edges, can be altered by using the
Polarity LLC pin.
Table 165. LLC_PAD_SEL Function
LLC_PAD_SEL[2:0]
000 (default)
101
10
Data Port Pins P[15:0]
P[15:8]
Y[7:0]
YCrCb[7:0]
9
2
C write allows the user to select between the
8
Description
Output nominal 27 MHz LLC on LLC1 pin.
Output nominal 13.5 MHz LLC on LLC1 pin.
Description
No swapping.
Swap Cr and Cb values.
7
Reserved. Do not use.
6
P[15: 0]
5
P[7: 0]
CrCb[7:0]
Three-State
CrCb[7:0] OUT
4
3
2
ADV7181
1
0