ADV7181BCP Analog Devices Inc, ADV7181BCP Datasheet - Page 21

• Manufacturer Part Number: ADV7181BCP
• Description: IC VIDEO DECODER NTSC 64-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7181BCP

• Applications: Recorders, Set-Top Boxes
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Adc/dac Resolution: 9b
• Screening Level: Industrial
• Package Type: LFCSP EP
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-ADV7181BEB - BOARD EVALUATION FOR ADV7181
• Lead Free Status / RoHS Status: Compliant, Contains lead / RoHS non-compliant

SYNC PROCESSING
The ADV7181 extracts syncs embedded in the video data
stream. There is currently no support for external HS/VS
inputs. The sync extraction has been optimized to support
imperfect video sources, for example, videocassette recorders
with head switches. The actual algorithm used employs a coarse
detection based on a threshold crossing followed by a more
detailed detection using an adaptive interpolation algorithm.
The raw sync information is sent to a line-length measurement
and prediction block. The output is then used to drive the
digital resampling section to ensure that the ADV7181 outputs
720 active pixels per line.
The sync processing on the ADV7181 includes two specialized
postprocessing blocks that filter and condition the raw sync
information retrieved from the digitized analog video.
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VBI DATA RECOVERY
The ADV7181 can retrieve the following information from the
input video:
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The ADV7181 is capable of automatically detecting the
incoming video standard with respect to color subcarrier
frequency, field rate, and line rate.
It can configure itself to support PAL-BGHID, PAL-M/N,
PAL-combination N, NTSC-M, NTSC-J, SECAM 50 Hz/60 Hz,
NTSC4.43, and PAL60.
VSYNC processor. This block provides extra filtering of the
detected VSYNCs to give improved vertical lock.
HSYNC processor. The HSYNC processor is designed to
filter incoming HSYNCs that have been corrupted by
noise, providing much improved performance for video
signals with stable time base but poor SNR.
Wide-screen signaling (WSS)
Copy generation management system (CGMS)
Closed caption (CC)
Macrovision protection presence
EDTV data
Gemstar-compatible data slicing
Rev. B | Page 21 of 104
GENERAL SETUP
Video Standard Selection
The VID_SEL[3:0] register allows the user to force the digital
core into a specific video standard. Under normal circumstances,
this should not be necessary. The VID_SEL[3:0] bits default to
an autodetection mode that supports PAL, NTSC, SECAM, and
variants thereof.
Refer to the Autodetection of SD Modes section for more
information on the autodetection system.
Autodetection of SD Modes
In order to guide the autodetect system of the ADV7181,
individual enable bits are provided for each of the supported
video standards. Setting the relevant bit to 0 inhibits the
standard from being detected automatically. Instead, the system
picks the closest of the remaining enabled standards. The results
of the autodetection can be read back via the status registers.
See the Global Status Registers section for more information.
Table 29. VID_SEL Function
VID_SEL[3:0]
Address 0x00 [7:4]
0000 (default)
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
Autodetect (PAL BGHID) <–> NTSC J
(no pedestal), SECAM.
Autodetect (PAL BGHID) <–> NTSC M
(pedestal), SECAM.
Autodetect (PAL N) <–> NTSC J (no
pedestal), SECAM.
Autodetect (PAL N) <–> NTSC M
(pedestal), SECAM.
NTSC J (1)
NTSC M (1).
PAL60.
NTSC4.43 (1).
PAL BGHID.
PAL N (= PAL BGHID (with pedestal)).
PAL M (without pedestal).
PAL M.
PAL combination N.
PAL combination N (with pedestal).
SECAM.
SECAM (with pedestal).
ADV7181