PCA9500D,112 NXP Semiconductors, PCA9500D,112 Datasheet - Page 10

IC I/O EXPANDER I2C 8B 16SOIC

PCA9500D,112

Manufacturer Part Number
PCA9500D,112
Description
IC I/O EXPANDER I2C 8B 16SOIC
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCA9500D,112

Interface
I²C, SMBus
Number Of I /o
8
Interrupt Output
No
Frequency - Clock
400kHz
Voltage - Supply
2.5 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (0.300", 7.5mm Width)
Includes
EEPROM, POR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-1024-5
935271533112
PCA9500D
NXP Semiconductors
8. Characteristics of the I
PCA9500_4
Product data sheet
8.1.1 START and STOP conditions
8.1 Bit transfer
The I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see
Fig 15. Bit transfer
Fig 16. Definition of START and STOP conditions
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
SDA
SCL
START condition
2
SDA
SCL
Figure
C-bus
S
Rev. 04 — 15 April 2009
16).
8-bit I
data valid
data line
stable;
2
C-bus and SMBus I/O port with 2-kbit EEPROM
Figure
allowed
change
of data
15).
STOP condition
mba607
PCA9500
P
© NXP B.V. 2009. All rights reserved.
mba608
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