PCA9500D,112 NXP Semiconductors, PCA9500D,112 Datasheet - Page 7

• Manufacturer Part Number: PCA9500D,112
• Description: IC I/O EXPANDER I2C 8B 16SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9500D,112

• Interface: I²C, SMBus
• Number Of I /o: 8
• Interrupt Output: No
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Includes: EEPROM, POR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1024-5; 935271533112; PCA9500D

NXP Semiconductors
PCA9500_4
Product data sheet
Fig 9.
Transient pull-up current (I
SDA
IO3 output voltage
IO3 pull-up output current
SCL
7.4.1.1 Byte write
7.3.1 Quasi-bidirectional I/Os
S
7.4.1 Write operations
START condition
7.4 Memory operations
slave address (I/O expander)
1
0
2
1
A quasi-bidirectional I/O can be used as an input or output without the use of a control
signal for data direction. At power-on the I/Os are HIGH. In this mode, only a current
source to V
heavily loaded outputs. These devices turn on when an output is written HIGH, and are
switched off by the negative edge of SCL. The I/Os should be HIGH before being used as
inputs. See
Write operations require an additional address field to indicate the memory address
location to be written. The address field is eight bits long, providing access to any one of
the 256 words of memory. There are two types of write operations, ‘byte write’ and
‘page write’.
Write operation is possible when the Write Control pin (WC) is put at a LOW logic level (0).
When this control signal is set at 1, write operation is not possible and data in the memory
is protected.
‘Byte write’ and ‘page write’ explained below assume that WC is set to 0.
To perform a byte write the START condition is followed by the memory slave address and
the R/W bit set to 0. The PCA9500 will respond with an acknowledge and then consider
the next eight bits sent as the word address and the eight bits after the word address as
the data. The PCA9500 will issue an acknowledge after the receipt of both the word
address and the data. To terminate the data transfer the master issues the STOP
condition, initiating the internal write cycle to the non-volatile memory. Only write and read
operations to the quasi-bidirectional I/Os are allowed during the internal write cycle.
3
0
4
0 A2 A1 A0
5
6
DD
Figure
7
OHt
R/W
is active. An additional strong pull-up to V
8
0
) while IO3 changes from LOW to HIGH and back to LOW
9
A
acknowledge
from slave
9.
Rev. 04 — 15 April 2009
data to port
IO3
8-bit I
1
2
C-bus and SMBus I/O port with 2-kbit EEPROM
I
OHt
A
acknowledge
from slave
data to port
DD
IO3
0
allows fast rising edges into
I
PCA9500
A
OH
acknowledge
from slave
© NXP B.V. 2009. All rights reserved.
002aae593
P
STOP
condition
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