PCA9500D,112 NXP Semiconductors, PCA9500D,112 Datasheet - Page 8

• Manufacturer Part Number: PCA9500D,112
• Description: IC I/O EXPANDER I2C 8B 16SOIC
• Manufacturer: NXP Semiconductors

Specifications of PCA9500D,112

• Interface: I²C, SMBus
• Number Of I /o: 8
• Interrupt Output: No
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Includes: EEPROM, POR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1024-5; 935271533112; PCA9500D

NXP Semiconductors
PCA9500_4
Product data sheet
Fig 10. Byte write
Fig 11. Page write
SDA
S
START condition
SDA
7.4.1.2 Page write
7.4.2.1 Current address read
1
slave address (memory)
7.4.2 Read operations
S
START condition
0
1
1
slave address (memory)
0
A page write is initiated in the same way as the byte write. If after sending the first word of
data, the STOP condition is not received, the PCA9500 considers subsequent words as
data. After each data word the PCA9500 responds with an acknowledge and the two least
significant bits of the memory address field are incremented. Should the master not send
a STOP condition after four data words, the address counter will return to its initial value
and overwrite the data previously written. After the receipt of the STOP condition the
inputs will behave as with the byte write during the internal write cycle.
PCA9500 read operations are initiated in an identical manner to write operations with the
exception that the memory slave address R/W bit is set to ‘1’. There are three types of
read operations: current address read, random read and sequential read.
The PCA9500 contains an internal address counter that increments after each read or
write access and as a result, if the last word accessed was at address ‘n’, then the
address counter contains the address ‘n + 1’.
When the PCA9500 receives its memory slave address with the R/W bit set to one it
issues an acknowledge and uses the next eight clocks to transmit the data contained at
the address stored in the address counter. The master ceases the transmission by issuing
the STOP condition after the eighth bit. There is no ninth clock cycle for the acknowledge.
See
0 A2 A1 A0
1
Figure
0 A2 A1 A0
R/W
12.
0
A
acknowledge
from slave
R/W
0
A
acknowledge
from slave
word address
Rev. 04 — 15 April 2009
word address
8-bit I
A
acknowledge
from slave
2
C-bus and SMBus I/O port with 2-kbit EEPROM
data to memory
A
acknowledge
from slave
DATA n
acknowledge
from slave
data
acknowledge
from slave
A
Write to the memory is performed.
A
data to memory
P
STOP condition.
Write to the memory
is performed.
DATA n + 3
acknowledge
PCA9500
002aae594
© NXP B.V. 2009. All rights reserved.
STOP condition.
from slave
002aae595
A
P
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