DS92LV16TVHG/NOPB National Semiconductor, DS92LV16TVHG/NOPB Datasheet - Page 13

• Manufacturer Part Number: DS92LV16TVHG/NOPB
• Description: IC SERDES LVDS 16BIT BUS 80-LQFP
• Manufacturer: National Semiconductor

Specifications of DS92LV16TVHG/NOPB

• Function: Serializer/Deserializer
• Data Rate: 2.56Gbps
• Input Type: LVTTL/LVCMOS
• Output Type: LVTTL, LVCMOS
• Number Of Inputs: 1
• Number Of Outputs: 16
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• No. Of Inputs: 16
• No. Of Outputs: 16
• Supply Voltage Range: 3.15V To 3.45V
• Driver Case Style: QFP
• No. Of Pins: 80
• Msl: MSL 3 - 168 Hours
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 1280Mbps
• For Use With: BLVDS16EVK - BOARD EVAL FOR DS92LV16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DS92LV16TVHG; *DS92LV16TVHG/NOPB; DS92LV16TVHG

Functional Description
The DS92LV16 combines a serializer and deserializer onto a
single chip. The serializer accepts a 16-bit LVCMOS or
LVTTL data bus and transforms it into a BLVDS serial data
stream with embedded clock information. The deserializer
then recovers the clock and data to deliver the resulting
16-bit wide words to the output.
The device has a separate Transmit block and Receive block
that can operate independent of each other. Each has a
power down control to enable efficient operation in various
applications. For example, the transceiver can operate as a
standby in a redundant data path but still conserve power.
The part can be configured as a Serializer, Deserializer, or
as a Full Duplex SER/DES.
The DS92LV16 serializer and deserializer blocks each has
three operating states. They are the Initialization, Data
Transfer, and Resynchronization states. In addition, there
are two passive states: Powerdown and TRI-STATE.
The following sections describe each operation mode and
passive state.
Initialization
Before the DS92LV16 sends or receives data, it must initial-
ize the links to and from another DS92LV16. Initialization
refers to synchronizing the Serializer’s and Deserializer’s
PLL’s to local clocks. The local clocks must be the same
frequency or within a specified range if from different
sources. After the Serializers synchronizes to the local
clocks, the Deserializers synchronize to the Serializers as
the second and final initialization step.
Step 1: When V
rializer, the respective outputs are held in TRI-STATE and
internal circuitry is disabled by on-chip power-on circuitry.
When V
begins locking to a local clock. For the Serializer, the local
clock is the transmit clock, TCLK. For the Deserializer, the
local clock is applied to the REFCLK pin. A local on-board
oscillator or other source provides the specified clock input
to the TCLK and REFCLK pin.
The Serializer outputs are held in TRI-STATE while the PLL
locks to the TCLK. After locking to TCLK, the Serializer block
is now ready to send data or synchronization patterns. If the
SYNC pin is high, then the Serializer block generates and
sends the synchronization patterns (sync-pattern).
The Deserializer output will remain TRI-STATE while its PLL
locks to the REFCLK. Also, the Deserializer LOCK output will
remain high until its PLL locks to an incoming data or sync-
pattern on the RIN pins.
Step 2: The Deserializer PLL must synchronize to the Seri-
alizer to complete the initialization. The Serializer that is
generating the stream to the Deserializer must send random
(non-repetitive) data patterns or sync-patterns during this
step of the Initialization State. The Deserializer will lock onto
sync-patterns within a specified amount of time. The lock to
random data depends on the data patterns and therefore,
the lock time is unspecified.
In order to lock to the incoming LVDS data stream, the
Deserializer identifies the rising clock edge in a sync-pattern
and after 150 clock cycles will synchronize. If the Deserial-
izer is locking to a random data stream from the Serializer,
then it performs a series of operations to identify the rising
clock edge and locks to it. Because this locking procedure
depends on the data pattern, it is not possible to specify how
long it will take. At the point where the Deserializer’s PLL
CC
reaches V
CC
is applied to both Serializer and/or Dese-
CC
OK (2.2V) the PLL in each device
13
locks to the embedded clock, the LOCK pin goes low and
valid data appears on the output. Note that the LOCK signal
is synchronous to valid data appearing on the outputs.
The user’s application determines whether sync-pattern or
lock to random data is the preferred method for synchroni-
zation. If sync-patterns are preferred, the associated deseri-
alizers LOCK pin is a convenient way to provide control of
the SYNC pin.
Data Transfer
After initialization, the DS92LV16 Serializer is able to transfer
data to the Deserializer. The serial data stream includes a
start bit and stop bit appended by the serializer, which frame
the sixteen data bits. The start bit is always high and the stop
bit is always low. The start and stop bits also function as
clock bits embedded in the serial stream.
The Serializer block accepts data from the DIN0-DIN15 par-
allel inputs. The TCLK signal latches the incoming data on
the rising edge. If the SYNC input is high for 6 TCLK cycles,
the DS92LV16 does not latch data on the DIN0-DIN15.
The Serializer transmits the data and clock bits (16+2 bits) at
18 times the TCLK frequency. For example, if TCLK is 60
MHz, the serial rate is 60 X 18 = 1080 Mbps. Since only 16
bits are from input data, the serial ’payload’ rate is 16 times
the TCLK frequency. For instance, if TCLK = 60 MHz, the
payload data rate is 60 X 16 = 960 Mbps. TCLK is provided
by the data source and must be in the range of 25 MHz to 80
MHz.
When the Deserializer channel synchronizes to the input
from a Serializer, it drives its LOCK pin low and synchro-
nously delivers valid data on the output. The Deserializer
locks to the embedded clock, uses it to generate multiple
internal data strobes, and then drives the recovered clock on
the RCLK pin. The RCLK is synchronous to the data on the
ROUT[0:15] pins. While LOCK is low, data on ROUT[0:15] is
valid. Otherwise, ROUT[0:15] is invalid.
ROUT[0:15], LOCK, and RCLK signals will drive a minimum
of three CMOS input gates (15pF total load) at a 80 MHz
clock rate. This drive capacity allows bussing outputs of
multiple Deserializers and multiple destination ASIC inputs.
REN controls TRI-STATE of the all outputs.
The Deserializer input pins are high impedance during Re-
ceiver Powerdown (RPWDN* low) and power-off (VCC =
0V).
Resynchronization
Whenever the Deserializer loses lock, it will automatically try
to resynchronize. For example, if the embedded clock edge
is not detected two times in succession, the PLL loses lock
and the LOCK pin is driven high. The Deserializer then
enters the operating mode where it tries to lock to random a
data stream. It looks for the embedded clock edge, identifies
it and then proceeds through the synchronization process.
The logic state of the LOCK signal indicates whether the
data on ROUT is valid; when it is low, the data is valid. The
system must monitor the LOCK pin to determine whether
data on the ROUT is valid. Because there is a short delay in
the LOCK signals response to the PLL losing synchroniza-
tion to the incoming data stream, the system must determine
the validity of data for the cycles before the LOCK signal
goes high.
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