DS92LV16TVHG/NOPB National Semiconductor, DS92LV16TVHG/NOPB Datasheet - Page 14

• Manufacturer Part Number: DS92LV16TVHG/NOPB
• Description: IC SERDES LVDS 16BIT BUS 80-LQFP
• Manufacturer: National Semiconductor

Specifications of DS92LV16TVHG/NOPB

• Function: Serializer/Deserializer
• Data Rate: 2.56Gbps
• Input Type: LVTTL/LVCMOS
• Output Type: LVTTL, LVCMOS
• Number Of Inputs: 1
• Number Of Outputs: 16
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• No. Of Inputs: 16
• No. Of Outputs: 16
• Supply Voltage Range: 3.15V To 3.45V
• Driver Case Style: QFP
• No. Of Pins: 80
• Msl: MSL 3 - 168 Hours
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 1280Mbps
• For Use With: BLVDS16EVK - BOARD EVAL FOR DS92LV16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DS92LV16TVHG; *DS92LV16TVHG/NOPB; DS92LV16TVHG

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Resynchronization
The user can choose to resynchronize to the random data
stream or to force fast synchronization by pulsing the Seri-
alizer SYNC pin. Since lock time varies due to data stream
characteristics, we cannot possibly predict exact lock time.
The primary constraint on the ’random’ lock time is the initial
phase relation between the incoming data and the REFCLK
when the Deserializer powers up. An advantage of using the
SYNC pattern to force synchronization is the ability for user
to predict the delay for PLL to regain lock. This scheme is left
up to the user discretion. One recommendation is to provide
a feedback loop using the LOCK pin itself to control the sync
request of the Serializer, which is the SYNC pin.
If a specific pattern is repetitive, the Deserializer’s PLL will
not lock in order to prevent the Deserializer to lock to the
data pattern rather than the clock. We refer to such pattern
as a repetitive multi-transition, RMT. This occurs when more
than one Low-High transition takes places in a clock cycle
over multiple cycles. This occurs when any bit, except DIN
15, is held at a low state and the adjacent bit is held high,
creating a 0-1 transition. The internal circuitry accomplishes
this by detecting more than one potential position for clock-
ing bits. Upon detection, the circuitry will prevent the LOCK
output from becoming active until the RMT pattern changes.
Once the RMT pattern changes and the internal circuitry
recognized the clock bits in the serial data stream, the PLL of
the Deserializer will lock, which will drive the LOCK output to
low and the output data ROUT will become valid.
Powerdown
The Powerdown state is a low power sleep mode that the
Serializer and Deserializer will occupy while waiting for ini-
tialization. You can also use TPWDN* and RPWDN* to re-
duce power when there are no pending data transfers. The
Deserializer enters Powerdown when RPWDN* is driven
low. In Powerdown, the PLL stops and the outputs go into
TRI-STATE, which reduces supply current to the µA range.
To bring the Deserializer block out of the Powerdown state,
the system drives RPWDN* high. When the Deserializer
exits Powerdown, it automatically enters the Initialization
state. The system must then allow time for Initialization
before data transfer can begin.
The TPWDN* driven to a low condition forces the Serializer
block into low power consumption where the supply current
is in the µA range. The Serializer PLL stops and the output
goes into a TRI-STATE condition.
To bring the Serializer block out of the Powerdown state, the
system drives TPWDN* high. When the Serializer exits Pow-
erdown, its PLL must lock the TCLK before it is ready for the
Initialization state. The system must then allow time for
Initialization before data transfer can begin.
TRI-STATE
When the system drives the REN pin low, the Deserializer
output enter TRI-STATE. This will TRI-STATE the receiver
output pins (ROUT[0:15]) and RCLK. When the system
drives REN high, the Deserilaizer will return to the previous
state as long as all other control pins remain static (RP-
WDN*).
When the system drives the DEN pin low, the Serializer
output enters TRI-STATE. This will TRI-STATE the LVDS
output. When the system drives the DEN signal high, the
(Continued)
14
Serializer output will return to the previous state as long as
all other control and data input pins remain in the same
condition as when the DEN was driven low.
Loopback Test Operation
The DS92LV16 includes two Loopback modes for testing the
device functionality and the transmission line continuity. As-
serting the Line Loopback control signal connects the serial
data input (RIN+/−) to the serial data output (DO+/−) and to
the parallel data output (ROUT[0:15]). The serial data goes
through deserializer and serializer blocks.
Asserting the Local Loopback control signal connects the
parallel data input (DIN[0:15]) back to the parallel data out-
put (ROUT[0:15]). The connection route includes all the
functional blocks of the SER/DES Pair. The serial data out-
put (DO+/−) is automatically disabled during the Local Loop-
back operating mode.
Application Information
Using the DS92LV16
The DS92LV16 combines a Serializer and a Deserializer into
a single chip that sends 16 bits of parallel TTL data over a
serial Bus LVDS link up to 1.28 Gbps. Serialization of the
input data is accomplished using an onboard PLL at the
Serializer which embeds two clock bits with the data. The
Deserializer uses a separate reference clock (REFCLK) and
an onboard PLL to extract the clock information from the
incoming data stream and deserialize the data. The Deseri-
alizer monitors the incoming clock information to determine
lock status and will indicate loss of lock by raising the LOCK
output.
Power Considerations
All CMOS design of the Serializer and Deserializer makes
them inherently low power devices. Additionally, the constant
current source nature of the LVDS outputs minimize the
slope of the speed vs. I
Powering Up the Deserializer
The REFCLK input can be running before the Deserializer is
powered up and it must be running in order for the Deseri-
alizer to lock to incoming data. The Deserializer outputs will
remain in TRI-STATE until the Deserializer detects data
transmission at its inputs and locks to the incoming stream.
Noise Margin
The Deserializer noise margin is the amount of input jitter
(phase noise) that the Deserializer can tolerate and still
reliably receive data. Various environmental and systematic
factors include:
out-of-band noise)
For typical receiver noise margin, please see Figure 16 .
Recovering from LOCK Loss
In the case where the Serializer loses lock during data
transmission up to 5 cycles of data that was previously
received can be invalid. This is due to the delay in the lock
detection circuit. The lock detect circuit requires that invalid
clock information be received 2 times in a row to indicate
loss of lock. Since clock information has been lost it is
possible that data was also lost during these cycles. When
the Deserializer LOCK pin goes low, data from at least the
previous 5 cycles should be resent upon regaining lock.
Serializer: TCLK jitter, V
Media: ISI, V
Deserializer: V
CM
CC
noise
noise
CC
curve of CMOS designs.
CC
noise (noise bandwidth and